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Control Unit Operation - Coggle Diagram
Control Unit Operation
Micro-Operations
The Fetch Cycle
4 registers
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
Fetch Sequence (symbolic)
Clock Cycle Grouping
The Indirect Cycle
The Interrupt Cycle
The Execute Cycle
ADD
ISZ
BSA
The Instruction Cycle
Instruction cycle code (ICC)
00: Fetch
01: Indirect
10: Execute
11: Interrupt
Control of the Processor
Functional Requirements
Define basic elements of processor
ALU
Registers
Internal data paths
External data paths
Control Unit
Describe micro-operations processor performs
Transfer data between registers
Transfer data from register to external
Transfer data from external to register
Perform arithmetic or logical ops
Determine functions control unit must perform
Sequencing (flow control)
Execution
Control Signals
Inputs
Clock
Instruction register
Op-code for current instruction
Flags
State of CPU
Results of previous operations
From control bus
Interrupts
Acknowledgements
Output
Within CPU
Via control bus
To memory
To I/O modules
A Control Signals Example
Fetch
Indirect
Interrupt
Internal Processor Organization
Gates
Control signals
Temporary registers
The Intel 8085
Incrementer/decrementer address latch
Interrupt control
Serial I/O control
Hardwired Implementation
Control Unit Inputs
Flags and control bus
Instruction register
Clock
Control Unit Logic