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REDUCED INSTRUCTION SET COMPUTERS (RISC) - Coggle Diagram
REDUCED INSTRUCTION SET COMPUTERS (RISC)
Instruction Execution Characteristics
Characteristics
Operands used
Execution sequencing
Operations performed
Instruction Sets
Operation
Movement of data
Sequence control
Operand
Mainly local scalar variables
Accessing local variables
Procedure Calls
Very time consuming
parameters passed
level of nesting
program remains confined to a rather narrow
window of procedure-invocation depth
Most variables are local
Implications
Best support is given by optimizing most used
and most time consuming features
Large number of registers
Careful design of pipelines
Simplified instruction set
Large Register File
Register Windows
organize the registers in such a fashion that should decrease the need to access memory
Global Variables
does not address the need to store global variables
Compiler Based Register Optimization
The essence of the optimization task is to decide which quantities are to be assigned to registers at any given point in the program
Graph Coloring
Adjacent nodes have different colors
Use minimum number of colors
Assign a color to each node
Reduced Instruction Set Architecture
CISC
harder to exploit
More difficult optimization
More complex control unit
RISC Characteristics
Register-to-register operations
Simple addressing modes
One instruction per cycle
Simple addressing modes
RISC Pipelining
Pipelining with Regular Instructions
Calculate the effective address
Fetch the operands from memory
Decode the instruction
Execute the instruction
Fetch instruction from memory
Store the result in the proper place
Optimization of Pipelining
Delayed Load
Loop Unrolling
Delayed Branch
MIPS R4000
One of the first commercially available RISC chip sets was developed by MIPS Technology Inc. The system was inspired by an experimental system, also using the name MIPS, developed at Stanford
Instruction Set
Instruction Pipeline
Instruction execute
Data cache first
Register file
Data cache second
Instruction fetch second half
Tag check
Instruction fetch first half
Write back
SPARC
An architecture defined by Sun
Microsystems
Register Set
Instruction Set
RISC vs CISC Controversy
several probelms attempting such comparison
There is no pair of RISC and CISC machines that are comparable
No definitive test set of programs exists
It is difficult to sort out hardware effects from effects due to skill in compiler
writing
Most of the comparative analysis on RISC has been done on “toy” machines
rather than commercial products