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Semiconductor Package - Coggle Diagram
Semiconductor
Package
Package Size
Small Outline (<10mm Each Side)
Others
Medium Outline (10-20 mm)
Large Outline >20 mm
Functionality
Optoelectronics
Others
RF and Microwave
Logic Packaging
Signal Conditioning
Memory Packaging
Power Management
Applications
Consumer Electronics
Others
Telecommunications
Medical Devices
Automotive
Aerospace and Defense
Package Type
Small Outline Integrated Circuit (SOIC)
Through-Hole Package
Surface-Mount Package
Ball Grid Array (BGA)
Embedded Wafer Level Ball Grid Array (EWLB)
Quad Flat Package (QFP)
Dual in-Line Package (DIP)
Plastic Leaded Chip Carrier (PLCC)
Flip-Chip Package
Wafer-level package (WLP)
Stacked Packages
Fan-Out Wafer-Level Packaging (FOWLP)
System-On-Package (SOP)
Package-In-Package (PIP)
System-In-Package (SIP)
Multi-Chip Module (MCM)
Chip-On-Board (COB)
Package-On-Package (POP)
3D Packaging
Flat Type Package
Others
Material
Others
Ceramic Package
Plastic Package
Metal Package
Interconnect
Copper Pillar
Wire Bonding
Others
Redistribution Layer (RDL)
Flip-Chip Interconnect
Through-Silicon Via (TSV)
Bonding/Attaching/Encapsulate Semiconductors
Die Attach Adhesives
Underfill
Adhesives
Epoxies
Acrylics
Cyanoacrylates
Urethanes