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PDP11 System - Coggle Diagram
PDP11 System
Memory
consecutive bytes
Word format
16 bit, LSB, MSB
octal representation
two bytes
address structure
address full word
address low byte
address high byte
address assignemtn
memory location
28K words without memory management
124K words with memory management unit
IO registers
in upper 4K words memory
CPU registers
in upper 4K words memory
total 128K words or 256 bytes
memory mapping
trap and interrupt vectors
000-037: 8 trap vectors
040-337: interrupt vectors
hardware stack
user programs
system utils, etc
memory operations
structure
buffer register
control register
address selected register
memory
DATI
DATIP
DATO
DATOB
available memory
core memory
semiconductor memory
ROM
UniBus
addresses
upper 4K addresses for IO and CPU registers
others for memory locations
Bus communication
master/slave relationship
dynamic control
interlocked dialog
Bus cycle
Interrupts
INTR
Data transaction
Transfer Type
DATO
DATOB
DATI
DATIP
MSYN, SSYN
Priority structure
vertical
from lowest to highest, BR4..BR7, NPR
horizontal
The nearer from CPU, the higher the priority
CPU
Arithmetic and Logic operation
Move data from or to or between IO or Memory
Composition
Unibus Control
priority arbitration
communication between CPU and external devices
Data manipulation
Decode all instructions
Arithmetic and logic operation
coordinate all cpu activities
structure
BAR
BR
IR
ALU
Process
ROM states
Fetch
Source
Destination
Execute
Trap hardware
General regsiters
PSW
16bit
IO
Interface
IO registers
Device