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CH7 Flip flops: - Coggle Diagram
CH7 Flip flops:
D - type:
The outputs flip flop between falling or rising edges:
Active Low Flip Flops changes with falling edges
Flops change with rising edges
Data pin: Additional enable pin (lock acts as enable pin for data pin)
Clock acts as a value for the data signal
D type can have multiple inputs:
Set, Reset, Data and Clock:
Data works is dependent on Clock, reset and set are independent. It needs to wait for the next clock pulse to change its output
Set and reset work above the clock and can directly change the output Q (Asynchronous)
Set H -> Q H
Reset H -> Q L
Set and Reset H -> Q ??? Future states become unpredictable
SR flips can be active low or high
Active High: Postive logic
Uses NOR gates:
0,0 yields 1
Set (H) -> Q (H)
Set (L) -> Q does not change
Reset (H) -> Q returns to (L)
If Reset and Set are both on -> Invalid
Active Low: Negative logic
1, 1 yields 0
Inputs are normally high:
Set (L) -> Q (H)
Set (H) -> Q does not change
Reset (L) -> Q returns to (L)
SR latches can be Gated too!
SR latches are can have an enable pin. This enable pin will determine if the S and R pins can change the result.
2 AND gates will determine if the S and R latches are in use
JK flip flops
2 NAND gates with 3 inputs