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Fetch Decode Execute Cycle - Coggle Diagram
Fetch Decode Execute Cycle
assembly language
CPUs are programmed using Assembly Language - a Low Level Language - this is closer to machine code (binary) than High Level Languages such as Python
common instructions
Common instructions include ADD, SUBTRACT, LOAD, STORE,, INPUT, OUTPUT
instruction set
All CPUs have an Instruction Set - a list of valid instructions that it understands.
The instruction set is used during the decode and execute stages of the FDE cycle.
Clock speed
number of instructions that can be processed per second by the CPU
where does the cpu get its instructions from?
Software (programs) provide the CPU with instructions, telling it what to do next.
The software is loaded, by the operating system, into main memory (RAM)
There can be more than one program running in main memory at any given time (they take turns executing their instructions in the CPU).
how are instructions processed?
To process an instruction, the CPU will go through the ‘fetch-decode-execute cycle’ – every single time!
fetch
The program is loaded into RAM by the operating system.
The operating system notifies the CPU where it can find the first instruction in RAM.
This location is loaded into the program counter and the fetch cycle begins
So let’s assume that our program’s first instruction is stored in RAM at location 305.
The program counter is updated with this location
As this is the first instruction to be fetched, nothing has happened so far and so the accumulator register is set to 0.
If the program had been running for a while then the accumulator would probably contain a different value
The address location in the program counter is copied into the memory address register (MAR)
Next the control unit loads the address from the MAR onto the address bus.
RAM then reads the contents of the address bus and then looks up the content stored at that location
The content, (in this case an instruction saying ‘add #5’) is then loaded onto the data bus.
The instruction (add #5) is passed across the data bus and copied into the memory data register (MDR).
Next, the instruction in the MDR is copied into the instruction register
The program counter is now incremented by one location – i.e. it changes from 305 to 306.
When program counter is incremented by one location, that means it is the end of the fetch cycle
execute
Once the instruction has been decoded and accepted as valid then the final part of the cycle, execute, can begin.
LOAD copies data from RAM into the ACC (via the data bus and MDR)
STORE copies data from the ACC into RAM (via the MDR and data bus)
Calculations are processed by the ALU
The ALU will read the original value of the ACC. Then it will process the instruction i.e. ADD #5.
It will then store the result of the calculation in the ACC.
decode
The control unit reads the contents of the instruction register – in this case ADD #5
It checks that this is a valid instruction i.e. it is part of its instruction set.
Each type of CPU has its own instruction set that the control unit understands. For example, this CPU knows what the instruction ‘ADD’ means.
If for some reason the instruction was not part of the CPU’s instruction set, e.g. SPGH#123 then it would not recognise it.
If this were to happen then the program has probably been corrupted and it will crash.
opcode
Each instruction consists of an opcode (the instruction itself e.g. ADD)
operand
operand (the data or the memory location of the data)