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CH9: Main Memory - Coggle Diagram
CH9: Main Memory
Background
RAM (memory)
Protection
Base
Limit registers
Address Binding
Compile time
Load Time
Execution time
Hardware support
Address Space
Logical Address
Physical Address
Memory Management Unit (MMU)
Dynamic Loading
Dynamic Linking
Paging
Frames (for physical memory)
Pages (for logical memory)
Page Tables
page number (p)
page offset (d)
Page-table base register (PTBR)
Page-table length register (PTLR)
Translation look-aside buffers (TLBs)
Address-space identifiers(ASIDs)
Shared Pages
Shared code
Private code and data
Swapping
Backing store
Roll out, roll in
Transfer time
Pending I/O
Double buffering
Structure of the Page Table
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
Contiguous Memory Allocation
two partitions
Fragementation
External Fragmentation
Internal Fragmentation