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How do we partition code into the PS & PL. - Coggle Diagram
How do we partition code into the PS & PL.
PL
Areas of the PS computing that are ripe for parallel processing
Hardware acceleration
Hard core components in PL
xADC
parallel processing
instantiating IPs
Creating or interfacing with high-speed custom protocols that are not natively supported by the PS.
Heavy & fast computing
Torque vectoring
Deterministic Timing:
DSPs
Real-Time Sensor Interfacing
storing big data via DMA
AXI DMA)
e.g. to BRAM --> DDR
e.g. ADC data
E.g. datalogging for Liveview --> core1
PS
Default: PS for general-purpose computing
Peripherals
Handling complex software stacks like Linux
faster to develop programs
Decision making
This project and future iterations may need to re-partition the design some way through the
development process;
t a certain function is
more computationally demanding than first envisaged, and would benefit from hardware
acceleration.
Intro: partitionting
Non Real-Time Operation
vs
Real-Time Operation
soft real-time or hard real-time. I
Overall plan:
1 core for liveview & datalogging
core0 for general purpose and decision making
fpga
se figur
prev:
will be running a webpage of live data, transmitting it over Wi-Fi.
This will be designed using an embedded Linux variant, as creating a GUI and showcasing data is much easier and more flexible with Linux. Xilinx offers the PetaLinux Tools and Linux peripheral drivers, which can be used to ease the implementation of a Linux Distribution. AVNET also supplies a PetaLinux BSP for the PicoZed.
Eventually, a task will also be needed for Ethernet communication with the driverless computer. Received values are logged and sent to the central task. As the secondary core must have access to all relevant data for the live-view, these values may be put into a protected shared memory by the data logging task, which is then read by the secondary core
e implied overhead of communicating between the two parts of the system
The time taken to transfer data and instructions between software and hardware constitutes an additional latency that offsets the processing speed-up;
an implication of using Zynq, as compared to a discrete processor and FPGA, is that the communication overhead is low;