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Comp Sci - 1.1.1 - Coggle Diagram
Comp Sci - 1.1.1
1.1.1a
Little Man Computer Commands:
- INP - Input
- OUT - Output
- STA - Store ACC contents in memory.
- LDA - Loads contents of memory in ACC.
- ADD - Add currents contents to ACC contents.
- SUB - Subtract.
- BRA - Contents of ACC set to given address.
- BRP - If ACC contents >= 0, the PC is set to the given address.
- BRZ - PC is set to given address if ACC = 0.
- HLT - Stops executing.
Busses are sets of parallel wires connecting computer components. The width of a bus is the number of parallel wires and determines how many bits can be transferred simultaneously.
- Control Unit - Directs the flow of data throughout the CPU using command and control signals. It accepts an instruction, decodes it and handles its execution.
- PC - Stores the address of the next instruction to be executed by the processor.
- MAR - Stores the address of the memory location from which data / an instruction is to be fetched from or written to memory.
- MDR - Holds the copy of the contents of the address specified by the MAR 9data fetched from memory).
- CIR - Holds the current instruction being executed. Splits the instruction into the opcode and the operand.
- ALU - Performs arithmetic and logical operations on data.
- ACC - A general purpose register that stores the result of any logic decisions or arithmetic operations.
- Address bus: Unidirectional
- Data bus - Bidirectional
- Control bus - Bidirectional
[Bus speed is measured in MHz]
1.1.1e
VNA:
- Shared memory for data and instructions.
- Single control unit.
- Cheaper develop due to simpler design.
- Two clock cycles needed to execute one instruction.
Harvard:
- Separate memory units for data and instructions.
- Separate data and address busses.
- Memory units can be of different sizes.
- Used commonly by RISC processors.
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MIMD: Multiple instructions carried out on multiple data items across several cores (used in general processing units).
1.1.1b
Fetch:
- PC contains address of the next instruction to be processed by the processor.
- Address is copies into MAR, it is then sent along the address bus.
- Control unit sends control signal along control bus.
- The instruction is retrieved at that address and is sent along the data bus to the MDR.
- It is copied into the CIR where it is split into its opcode and operand.
- The program counter increments.
Decode:
- The instruction is decoded by the decode unit in the CU.
Execute:
- The instruction is executed.
- The cycle is continuous.
1.1.1c
Clock speed:
- Number of clock cycles per second.
Cache:
- Stores copies of recent data or instructions.
- Quicker to access these than RAM (within processor).
Number of Cores:
- Increases the number of instructions that can be executed simultaneously.
1.1.1d
Pipelining is a way of boosting execution efficiency. One instruction will be executed while another is being decoded and another is being fetched.
Branch commands force the pipe to be flushed and so programs with many branch commands may not benefit from pipelining.