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FPGA - Coggle Diagram

- - - - Combo of MUX and DFF
    - - Parallelism vs. serialism
    - - N select pins, 2^N input pins & 1 outout
    - - Structural modelling
        
        Digital system of subsystems
        
        Block diagrams (component)
      - Dataflow Modelling
        
        Low level
        
        Logic gates
      - Behavioural modelling
        
        High-level description of what happens
        
        Via process(sensitivity)
        
        Sequential
      - VÆR LIGE OBS PÅ, OM VI IKKE HAR BYTTET OM PÅ DEFINITIONER
    - - Entity
        
        External view
      - Architecture
        
        Internal description --> entity's digital logic.
    - - Signal
        
        Physical memory
        
        Types
        
        bit, bit_vector
        
        boolean
        
        integer, natural, positiv
        
        character, string
        
        std_logic, vector
        
        signed, unsigned
        
        ARITHMETIC ONLY WORKS WITH INTEGER + SIGNED + UNSIGNED
        
        Directional Wire connection
      - Variable
        
        Software memory
        
        undirectional Wire connection???????
      - Tristate logic
      - Constants
    - - Switching quickly between enabling1 of 4 of the 7-segments
  - - - moore machine
        
        Output value is determined only by state
        
        Input has effect only on states
      - Mealy machine
        
        Outputs are triggered when transitioning
        
        Input sensitive
        
        Input has direct effect on states and outputs
        
        Usually has less states
  - - - Fraction of a second can lead to glitches
    - - One bit change at a time
- - - - Toggles every time it hits
  - - - 1 bit memory
- - - - Soft core
        
        Permit designers to modify design at functional level
      - Hard core
        
        Function cannot be majorly modified by designers
        
        --> Optimized
        
        Lower level desccription
        
        E.g ADC
  - - - Quantization
      - PP9 slide 7/8
      - 12 bit iflg PP13??? Eller er den 16?
      - Sampling
      - xADC
        
        EOC
        
        When conversion is done, EOC signal is produced
        
        DADDR
        
        Selects corresponding register number in regards to EOC
        
        DEN
        
        Digital Enable - needs to be assereted when DADDR finds reg number
        
        DRDY
        
        Data Ready - produced when data is ready at port
        
        DO
        
        Digital data can be captured at this port (Digital output???)
        
        PP22,PP25
        
        ER DENNE SINGLE-ENDED ELLER DIFFERENTIAL?
        
        Unipolar mode er default
        
        Sequencer mode
    - - Noise resistant
        
        Noise is added to both inverse signals at same time --> cancels
      - PP17 fra lek9
    - - Sends 1 line of the signal to the ADC
        
        Prone to noisse (SNR)
- - - - Stop '1' og Start '0' bit
      - data-frame
        
        Bits sendt afsted
      - BAUD rate
        
        must agree on sending speed
      - Receive
      - Transfer
        
        LSB First
        
        First bit to send is start = 0
        
        Last bit to send is ALWAYS stop bit = 1
      - Parity bit
        
        Odd
        
        1 taller inklusiv parity skal være ulige
        
        Even
        
        1 taller plus parity skal være lige
        
        None
        
        ingen parity
      - full-duplex, Async --> No clock between tx/rx og tovejs
      - Seriel kommunikation
  - - - Kan kommunikerer begge veje men en af gangen
    - - Envejs kommunikation
    - - Begge veje og samme tid