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1.1 Systems Architecture - Coggle Diagram

- - - - Address Bus Goes to memory to fetch the information and data bus takes information back to CPU
    - - Turns it into machine code
    - - Carries out the instruction
  - - - Holds the address of the next instruction
    - - Holds the address of the current instruction
    - - Holds the data currently being used
    - - Stores the results of calculations in the ALU
  - - - ROM, RAM and Cache
        
        Cache
        
        On the CPU
        
        Small amount of RAM
        
        3 Levels
        
        Level 3 is largest, least expensive and slowest
        Level 2 is middle size, medium expense and middle in speed Level 1 is smallest, most expensive and fastest
        
        Fast and expensive
    - - Controls signals to control the hardware
      - Moves data
      - Carries out F/D/E instructions
    - - Carries out arithmetic and logical operations
      - Arithmetic is +, -, *, /
      - Logic is AND , OR
    - - PC - Increase by one for each circuit of the FDE cycle
      - Small bit of memory which holds the memory temporarily
      - MAR - Holds the address of the instruction which is being fetched from the memory
      - MDR - Holds the instruction currently being processed
      - AC - Temporarily holds results of data/ instructions
      - CIR - Holds instruction
    - - Address Bus
        
        One way (Uni-directional)
        
        Goes to the address in the memory to fetch data
      - Data Bus
        
        Two way (Bi-directional)
        
        Takes data between CPU and RAM and CPU and ROM
        Used to pick up and store data
      - Control Bus
        
        Carrie the clocks pulses
        
        Two way (Bi-directional)
    - - 3 - 5 GHz (3 -5 billion instructions a second)
      - Pulse that controls the signals
  - - - Don't necessarily need CIR