1.1 Systems Architecture
Architecture of the CPU
Embedded Systems
Factors affecting
CPU performance
Characteristics
Examples
Clock speed
Number of Cores
Cache Size
Purpose of CPU
Von Neumann Architecture
Common Components
Fetch
Decode
Execute
Address Bus Goes to memory to fetch the information and data bus takes information back to CPU
Turns it into machine code
Carries out the instruction
PC - Program Counter
MAR - Memory Address Register
MDR - Memory Data Register
AC - Accumulator
Primary Memory
ROM, RAM and Cache
Holds the address of the next instruction
Holds the address of the current instruction
Holds the data currently being used
Stores the results of calculations in the ALU
PC
MAR
ADDRESS BUS
PRIMARY MEMORY
DATA BUS
MDR
CIR
CU
ALU
AC
To process data and instructions
Control rest of computer system
Control Unit
ALU - Arithmetic Logic Unit
Registers
Controls signals to control the hardware
Moves data
Carries out F/D/E instructions
Carries out arithmetic and logical operations
Arithmetic is +, -, *, /
Logic is AND , OR
PC - Increase by one for each circuit of the FDE cycle
Small bit of memory which holds the memory temporarily
MAR - Holds the address of the instruction which is being fetched from the memory
MDR - Holds the instruction currently being processed
Buses
Address Bus
Data Bus
AC - Temporarily holds results of data/ instructions
Two way (Bi-directional)
Takes data between CPU and RAM and CPU and ROM
Used to pick up and store data
One way (Uni-directional)
Goes to the address in the memory to fetch data
Cache
On the CPU
Small amount of RAM
3 Levels
Level 3 is largest, least expensive and slowest
Level 2 is middle size, medium expense and middle in speed Level 1 is smallest, most expensive and fastest
Fast and expensive
Clock
3 - 5 GHz (3 -5 billion instructions a second)
Pulse that controls the signals
Control Bus
Carrie the clocks pulses
Two way (Bi-directional)
Larger cache = Faster CPU as Cache is closer to CPU than RAM
Data & Instructions stored in binary in the primary memory
Data is fetched serially (one at a time)
Decodes and executes before cycling to next fetch
Higher clock speed = More FDE cycles a second = Faster CPU
CIR - Holds instruction
- Address in PC -> MAR
- Address in PC goes up by one
- Address bus travels to memory address
- Instruction / Data sent on Databus -> MDR
- I/D in MDR -> CIR
- I/D on CIR is decoded and executed
- Any results stored in the AC
- Back to 1. until no more
Don't necessarily need CIR
Actions may return data to storage