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COMP 273 Intro to Computer Systems - Coggle Diagram
COMP 273 Intro to Computer Systems
Number Representations
Integer
Signed Int: Two's Complement
Base Conversion
Real Number
Decimal to binary: multiply by 2
Floating Point (IEEE standard)
Fixed Point
Problem with Binary
Loss of precision
Overflow / Underflow
MIPS Assembly
Introducation
add, sub, addi
lw Reg, Offset(AddrReg)
Conditions
conditional branches: beq, bne
Jump to label: j label
pseudo-instructions: blt, bgt, ble, bge
Procedures
jal label + jr $ra : to call function and return
Push / Pop stack
Logical
Bitwise logical: and, or, nor
Mask with and & or
Logical Shift: sll, srl
Instruction Representation
Format J (jump)
Format R (Register)
Format I (immediate)
Linker & I/O
Assembler, Linker, Loader
Address management
Symbol Table
Relocation Table
Assembler resolves pseudo-instructions
I/O
Polling
Interrupt
CONTROL & DATA in I/O devices
Circuits & System Board
System Board
Timing
System Board Clock
CPU Clock
Addressing
Every component on the system board has a unique integer number that identifies it
Bus
Only 1 unit of data can use the bus at a time
Circuit
Diagram of AND, OR, NOT gates
Decoder: address selector
Encoder: used to generate binary code
Boolean Algebra
A or B: A+B (logical sum)
Derive boolean expression from truth table
A and B: AB (logical product)
Don't care
Simplify
Use boolean laws
Karnaugh Maps
Classical CPU
CPU structure
Sequencer (like an address selector)
Register
General purpose
Specific purpose
ALU
2's complement circuit
Status (zero, negative, overflow)
Half-adder & Full-adder (2 number and a carry)
RAM
D Flip-flop: the mechanics of saving a bit
8-bits Data
32-bits Address
Read / write mode bit
Micro Instructions
ADD, SUB, LW, SW, CMP, BEQ, JUMP...
[Machine] <-- Operation_Expr
IR: opcode + arguments
Micro Circuits
Use "step" code and adder to iterate over the steps
In each step, CU opens the correct gates, send the data in 1 clock cycle.
Use opcode and mode to select the correct instruction
Pipeline CPU
Cache Structures
I/O with devices
Interrupt
Use DMA (Direct Memory Access)
Polling
Faults
cache fault
When a "Miss" happen to the cache (can't find the data/instruction in the cache)
pipeline fault
A second instruction uses the register modified by the previous instruction
5 stages:
Load
ALU
Fetch
Data Cache
Store (register)