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Instruction-Level Paralellism and Superscalar Processors - Coggle Diagram
Instruction-Level Paralellism and Superscalar Processors
PENTIUM 4
Out-Of-Order Execution Logic
Register Renaming
Micro-Op Queueing
Allocate
Micro-Op Scheduling And Dispatching
Integer And Floating-Point Execution Units
Front End
Trace Cache Next Instruction Pointer
Trace Cache Fetch
Generations of Micro-Ops
Drive
ARM CORTEX-A8
Instruction Decode Unit
Integer Execution Unit
Instruction Fetch Unit
SIMD And Floating-Point Pipeline
Design Issues
Instruction Issue Policy
In-Order Issue With In-Order Completion
In-Order Issue With Out-Of-Order Completion
Out-Of-Order Issue With Out-Of-Order Completion
Register Renaming
Instruction-Level Paralellism and Machine Paralellism
Machine Paralellism
Branch Prediction
Superscalar Execution
Superscalar Implementation
Overview
Superscalar vs Superpipelined
Limitations
Procedural Dependancy
Resource Conflicts
True Data Dependancy
Output Dependancy
Antipendancy