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Stratix10 Basic - Coggle Diagram
Stratix10 Basic
MLABs = Memory LABs
ALM/s (Adaptive Logic Module/s)
LAB(Logic Array Block) = 10ALMs
Key Concept
K6: CDC/Synchronizers
K5: Clock Tree Synthesis
K3: Large Memory Pipelining
K7: High Fanout Signals/ Reset pipeline
K4: DSP Blocks
K1: Logic Depth/ Logic Levels
K2: Routing Congestion/ Chip Planner
K0: High-Performance Designs for S10
Incremental Block-Based Compilation
Intel_PSG:Online Training
Design Assistant GUI2021:
https://www.intel.com/content/www/us/en/programmable/customertraining/OLT/Timing_Closure_OH_02232021/Timing_Closure_OH_02232021.mp4
2021:
https://www.intel.com/content/www/us/en/programmable/customertraining/OLT/hyperopt_intro/hyperopt_intro.mp4
CDC2020:
https://www.intel.com/content/www/us/en/programmable/customertraining/OLT/CDC_Considerations/20_3/CDC_Considerations.mp4
中午资料
https://www.intel.cn/content/www/cn/zh/docs/programmable/683353/20-1/fpga-architecture-introduction.html
https://www.intel.cn/content/www/cn/zh/docs/programmable/683082/20-3/recommended-hdl-coding-styles.html