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CHAPTER 1.2 - CACHE MEMORY, ACCESS TIME, CAPACITY, <===================…
CHAPTER 1.2 - CACHE MEMORY
Memory Hierarchy
Defination
used in theory of computation when discussing performance issues in computer architectual design
Characteristics
capacity
Access time
cost
Cache Memory
internal memory and contains a copy of portions of main memory
How it works
Processor attempts to read a word of memory
A check is made to determine if the word is in the cache
YES
The word is delivered to the processor
NO
A block of main memory, consisting of some fixed number of words is read into the cache
Level of cache
CACHE LEVEL
L1
L2
L3
random access memory(RAM) that a computer microprocessor can access more quickly than it can access regular RAM
Cache/main memory structure
Mapping
Functions
fewer cache lines than main memory blocks, an algorithm is needed for mapping main memory blocks into cache lines
choice of mapping functions determine how the cache is organized
Techniques
Direct mapping
content of alocation in main memory can be stored at one and only one, specific location in the cache (it is mapped to exactly one location in the cache)
only one block in the cache that could possibly contain that information
maps each block of main memory into only one possible cache line
Assiciative mapping
permitting each main memory block to be loaded into any
line of the cache
flexibility as to which block to replace when a new block is read into the cache
each memory location can be in any cache block (a block is allowed to go anywhere in cache)
no restriction on mapping from memory to cache
Set Associative mapping
combines the ideas of Direct Mapped and Associative cache
allows that each word that is present in the cache can have two or more words in the main memory for the same index address
ACCESS TIME
FAST
SLOW
SLOWER
CAPACITY
SMALL
LARGE
VERY LARGE
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