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Semiconductor Value Chain - Coggle Diagram
Semiconductor Value Chain
Design (Fabless)
Software (EDA)
Companies
Cadence Design Systems (CDNS)
Synopsys (SNPS)
States: Used for almost every design 12nm & below
Features
R&D: Highest margins in industry - 35%
Closer relationship with fabs & eqpt mfg than Design
Must have deep knowledge of fab process / keep pace w/ short innovation process
Helps ^^ for researching & improving new process nodes
Highly concentrated, all in US
IP
Companies
ARM Holdings
IP Blocks
Entire process cores
Smaller - standard functionality (i.e. USB, networking interfaces)
Features
Cost to Design
2016 (10nm): $170MM
2020 (5nm): $540MM
ASIC: Hyperscalers design own (AAPL, AMZN, GOOGL, TSLA)
Fabless, EDA, IP work together with foundries to match a particular process node
Early in dev: fabless must decide on which process node from which fab to build chip
Companies
United States
Qualcomm (QCOM)
Broadcom (AVGO)
Nvidia (NVDA)
American Micro Devices (AMD)
Xilinx (XLNX) - being acquired by AMD
Taiwan
MediaTek
Novatek
Realtek
China (15%)
HiSilicon (sub of Huawei)
Fabrication
Equipment
Companies
Applied Materials (AMAT)
Plasma etching
ASML
Photolithography (doesn't compete w/ others)
Tokyo Electronics
Lam Research (LRCX)
KLA Corporation (KLAC)
Metrology eqpt for Quality Control
Chemicals ($40B TAM)
Features
KPI = Purity; impurity req of 1 part per billion (ppb)
Companies
BASF, Air Liquide, Air Products, Dupont, Fujifilm Holdings, JSR, LG Chem, Linde, Merck KGaA, Mitsui Chemicals, Shin-Etsu Chemical, Sumitomo, Taiwan Spec. Chem, Taiyo Nippon, Sanso, Tokyo, Ohka Kogyo
Wafer
Types
Silicon
300mm silicon wafers = standard for advanced chips (processors, SoC, Memory)
Gallium Arsenide (FaAs), Gallium Nitrate (GaN), and Silicon Carbide (SiC)
Features
Highly concentrated market
20 wafer suppliers in 1990, now 5 companies control 90% of market
Companies
Shin-Etsu
Leader: +30% market share
Sumco (~25%)
GlobalWafers (~17%)
Siltronic (~13%)
SK Siltron (12%)
Companies
Pure Play
TSMC (TSM)
50% Market Share
Samsung
Will invest $116B in foundry until 2030
Global Foundries
Stopped developing 7nm in 2018
United Microelectronics (UMC)
Semiconductor Manufacturing International Corp (SMIC)
Started 14nm in 2019; 90% of rev mature nodes (40-250nm)
Features
Cost to Build
TSMC 3nm: $19.5B
Need: 1) Capital, 2) Deep knowledge
Hundreds of process steps; dozens diff types of eqpt
Assembly & Testing (OSAT) - $9.4B
Equipment
Chemicals
Back-End Assembly ($3.7B)
Lithography
Back-End Lithography
Metrology & Inspection
Wafer Inspection
Die Inspection
Package Inspection
Back-End Metrology
Dicing
Blade Dicing, Laser Dicing, Plasma Dicing
Backside Grinding
Mounting
Package Singulation
Bonding
Die Attach
Wire Bond
Flip Chip / Mass Reflow
Advanced Packaging
Packaging
Molding & Sealing
Finishing & Marking
Package Inspection
Features
Manufacturing results in silicon wafer containing many small integrated circuits (dies) that must be cut out, tested, and packaged. Referred to as the "back-end"; wafer fab = "front end"
Labor intensive, lower margins
Market: Grew from $17B in 2009 to +$30B in 2019
New manu line cost: $100MM to $200MM
Consolidation: Top 20 = 92% market share in 2019; 70% in 2009
Companies
ASE Group (ASX) - Taiwan: 26% share
Amkor Tech (AMKR): 13% share, only OSAT in US
Kulicke and Soffa (KLIC)
Axcelis (ACLS)
Advanced Energy (AEIS)
Brooks Automation (BRKS)
Cohu (COHU)
Formfactor (FORM)
Icohr Holdings (ICHR)
nLIGHT (LASR)
Nova Measuring Instruments (NVMI)
Onto Innovation (ONTO)
Veeco Instruments (VECO)
Features
Innovative
Efficient
Not Resilient