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Integration's CoDe Map, Integration's CoDe Map, rpa_scripts -…

- - - - C5: Power Analysis &> PTC
      - C3: Fitter + = Plan > Place > Route > Retime > Finalize
      - C2: Analysis & Synthesis
      - C1: IP Ceneration &> Platform Designer
      - C4: Timing Analysis &>
      - C6: Reports: impl_run_x/results
      - C0: Sub-Module regression OK > LONER INT
    - - B1: Assignment Editor: Review settings
      - B0: Setting files: qsf / sdc / tcl / hex / rtl
    - - D4: Timing Analyzer: tcl
      - D5: Signal Tap Logic Analyzer & Rapid Compilation
      - D2: Chip Planner
      - D1: RTL Viewer
      - D3: Technology Map Viewer (Post-Mapping/Fitting)
      - D0: Quartus Prime GUI
    - - Timing +
        
        S5: Clock tree/region / Clock group / LLR / QDB / Back anno
        
        S6: SDC priority: false_path > clock_groups > skew / delay
        
        S7: Fast Forward Timing Closure Recommendations
        
        S8: Retiming Restrictions: Insuff.Regs / sdc exception ...
        
        S9: Multiseed Compilation Timing Reports
      - Settings +
        
        S1: Area / Utilization
        
        S2: Routability / Routing Congestion
        
        S0: Performance
        
        S3: Power
        
        S4: Compile Time ~ 10h+
      - STP-over-Eth
        
        E0: https://jiradc.ext.net.nokia.com/browse/LONER-1589/2796
        
        E1: SoCSW / SoClab adaptation
      - quartus_sh
- - - - C3: Fitter + = Plan > Place > Route > Retime > Finalize
      - C2: Analysis & Synthesis
      - C1: IP Ceneration &> Platform Designer
      - C4: Timing Analysis &>
      - C6: Reports: impl_run_x/results
      - C0: Sub-Module regression OK > LONER INT
      - C5: Power Analysis &> PTC
    - - B1: Assignment Editor: Review settings
      - B0: Setting files: qsf / sdc / tcl / hex / rtl
    - - D4: Timing Analyzer: tcl
      - D5: Signal Tap Logic Analyzer & Rapid Compilation
      - D2: Chip Planner
      - D1: RTL Viewer
      - D3: Technology Map Viewer (Post-Mapping/Fitting)
      - D0: Quartus Prime GUI
    - - S5: Clock tree/region / Clock group / LLR / QDB / Back anno
      - S6: SDC priority: false_path > clock_groups > skew / delay
      - S7: Fast Forward Timing Closure Recommendations
      - S8: Retiming Restrictions: Insuff.Regs / sdc exception ...
      - S9: Multiseed Compilation Timing Reports
    - - S1: Area / Utilization
      - S2: Routability / Routing Congestion
      - S0: Performance
      - S3: Power
      - S4: Compile Time ~ 10h+
    - - E0: https://jiradc.ext.net.nokia.com/browse/LONER-1589/2796
      - E1: SoCSW / SoClab adaptation