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Avengers' CoDe Picture, Avengers' CoDe Picture - Coggle Diagram
Avengers' CoDe Picture
Avengers' CoDe Picture
UVM basics
1.1
Book: SystemVerilog for Verification
1.2 Book: UVM 实战
Simulation-Lite
4.3 dl_path_full
4.3.1 tc_leka_tx_ingress_egress
4.3.2 tc_leka_tx_ingress
4.3.3 tc_leka_tx_ingress_cell_delete
4.3.4 tc_cti_bcn_change_monitor_hw_event
4.3.5 tc_leka_tx_l2_late_msg
4.3.6 tc_cti_pll_monitor_hw_event
4.9 Python TV parser
4.8 ethss_only
4.8.1 tc_ethss_bip_ingress
4.8.2 tc_ethss_bip_egress
4.8.3 tc_ethss_hp_ingress
4.8.4 tc_ethss_hp_egress
4.8.5 tc_ema_hw_event_sw_config
4.8.6 tc_ema_hw_event_timer-BCNC
4.8.7 tc_ema_hw_event_timer-CST
4.8.8 tc_ethss_bip_ingress_ema
4.8.9 tc_ethss_bip_egress_ema
4.2 no_stubs
4.2.1 tc_loner_sanity
4.2.2 tc_loner_reg_id
4.2.3 tc_loner_hps_2_mem
4.2.4 tc_cti_reset
4.2.5 tc_chip_id
4.2.6 tc_loner_pio_test
4.2.7 tc_temperature_sensor_test
4.2.8 tc_spi_integration_test
4.2.9 tc_loner_reg_test-xxx
4.2.10 tc_axi_burst-AXI_H2F
4.2.11 tc_axi_error-AXI_H2F
4.2.12 tc_axi_addr-AXI_H2F
4.2.13 tc_loner_reg_backdoor_test
4.2.14 tc_sysdma_reg_trig-xxx
4.2.15 tc_sysdma_perf-xxx
4.2.16 tc_bcnc_timer
4.2.17 tc_cst_timer
4.2.18 tc_ethss_mac_phy_access
4.7 cpriss_only
4.7.1 tc_cpriss_rx_rand-xxx
4.7.2 tc_cpriss_tx_rand-xxx
4.4 ul_path_basic
4.4.1 tc_leka_rx_insert
4.4.2 tc_cpri_to_ethss_test
4.4.3 tc_leka_rx_dynamic_configuration_monitor
4.1
SimLite - Simulation_Lite Overview
4.5 ul_path_radio_if
4.5.1 tc_leka_rx_ingress
4.5.2 tc_leka_rx_axi_stream_wd
4.5.3 tc_harq_ddr4_watchdog
4.5.4 tc_tf_capture
4.6 ul_path_full
4.6.1 tc_leka_rx_ingress_egress
How to run simulation
2.4 How to run CI
2.5 How to run Toggle coverage
2.1 How to run the first test case
2.2 How to run the first regression
2.3 How to register cases in QC
Simple top