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WAFERING - Coggle Diagram

- - - - Intrinsic (Pure Silicon)
      - Extrinsic
        
        N-type
        
        P-type
      - Growth method
        
        Liquid encapsulated method
        
        Bridgman-Stockbarger method
        
        Czochralski method (CZ)
        
        Float zone (FZ)
    - - Solar cells
      - PhotoSensor
      - Camera
    - - have a wide range of current and voltage handling capacity
      - It also requires low voltage during operation compared to vacuum tubes
      - can be used for the integration of complex but readily build-up microelectronic circuits.
    - - respond poorly in the high-frequency range.
      - can’t handle as much power as ordinary vacuum tubes do
  - - - Oxide coating method
        
        Atmospheric Thermal Oxide (ATOX)
        
        Dry Oxide
        
        PECVD Oxide
    - - Nitride coating method
        
        LPCVD
        
        low stress LPCVD
        
        PECVD
    - - Thin film oxide deposition
      - Lead based ferroelectric layers for uncooled thermal imagings
      - Preparation of complex ferroelectric oxides
    - - very hazardous. They are also even toxic and torming by products of these precursors are toxic.
      - They are also formed of highly toxic,hybride,gases due to formation of phosphine
    - - Photonic Devices
      - Etch mask and Etch stop layer in SOI
  - - - Substrate Carrier for MEMS
        
        Micro Mechanical System (MEMS)
      - Microfluid Chip for Biotechnology
        
        Instrument for DNA-extraction or Cell lysis
    - - transparent,it is much easier to observe any bonding defects that may occur during process develpoment
      - Low electrical loss (glass is an insulator)
      - Potential to optimize processes (glass wafers can be as thin as 100µm)
      - More cost effective
    - - It is a very costly material and has to be handled with care
  - - - High Performance Radio Frequency Insturment
        
        Radio Astronomy
        
        Handphones
        
        Satellites
      - High Performance Watches
        
        Casio G-Shock (Get power from sun and time from an atomic clock)
    - - Lower parasitic capacitance due to the upper silicon’s insulation from the bulk silicon substrate, which reduces power consumption.
      - have greater resistance to radiation, making them less prone to soft errors. The insulating layer also reduces current leakage, which increases their power efficiency.
      - reduced dependency on temperature and fewer antenna issues.
    - - the insulator may cause thermal issues because it is poor conductor of heat.
      - CDM/ESD is also worse in SOI as there are no parasitic diodes to supply or ground.
      - does not have n-well capacitance that means little less decoupling capacitance on supply. But this is not a significant penalty.
  - - - Kyropoulos method is a continuation of the Czochralski method (CZ)
      - Kr method allows for the production of very large ingots of single crystal sapphire that can then be processed into wafers.
    - - Hybrid Microelectronic Product
      - LED
      - Ideal material for substrate in growing III-V and II-VI compound.
        :
      - Ultra High Speed IC
    - - Notable Hardness and Durability: It is fundamentally harder than glass and it has a higher resistance to scratch unless it will come in contact with materials with similar or greater hardness
      - Wide Optical Transmission: Another advantage of sapphire crystal that makes it one of the best materials for use in windows and on the screens of consumer electronic devices is its high transparency to a wide range of wavelengths
      - Insulation and Conductivity: It has excellent electrical insulating properties or electrical resistance that makes it suitable for use as an insulating substrate in electronic components. Furthermore, despite being an insulator, Note that these specific properties make it a chemically and thermally stable material.
    - - Expensive Production Cost :This material is produced by subjecting aluminum oxide power to extreme heat and pressure. Note that its high melting point means that it also takes a tremendous amount of energy input for it to be melted and molded. This translates to high energy costs.
      - Still Susceptible to Shattering:Note that harder materials are more brittle. Heavy impacts such as falling from a height of three or more feet or hard and forceful impact to a solid surface can shatter brittle materials
      - Uneconomical in Some Applications :These devices have lifespans of 2 to 4 years which are shorter than the entire lifespan of a sapphire crystal. Consumers of smartphones often replace their devices with newer models. Furthermore, because of its high energy cost, its production can have a higher carbon footprint than glass.
  - - - reduced parasitic capacitance
      - improved linearity
      - lower power consumption compared to bulk silicon.
    - - effect of lateral stress
      - the non-homogenous region in the film
      - defects at the interface
    - - Temperature Sensors
      - Energy harvesting devices
        
        Piezoelectric
        
        Thermoelectric
- - - - The process converts polycrystalline silicon into samples with a single crystal orientation, known as ingots.
        
        Polysilicon mechanically broken into 1 to 3 nuggets and undergoes stringent surface etching and cleaning in a cleanroom environment
        
        These nuggets are then packed into quartz crucibles for meltdown in a CZ furnace at 1420°C.
        
        A nanocrystalline silicon seed is installed into a seed shaft in the furnace's upper chamber and slowly lowered until it dips approximately 2 mm into the silicon melt.
        
        The melt solidifies the boundary as the seed slowly retracts from the surface.
        
        Both the crucible and the seed are rotated in opposite directions as the seed draws silicon from the melt, allowing an almost round crystal to form.
        
        The seed lift is increased once the proper crystal diameter is achieved. The diameter of the crystal will be controlled by the heat transfer from the heater element.
        
        This gradual cooling allows the crystal lattice to stabilize and simplifies handling prior to transport to the next operation.
    - - Involves a series of preliminary mechanical and chemical process steps required to convert the ingot segment into a functional wafer.
        
        This technique is known as Multi-Wiring Slicing or Multi-Wire Sawing (MWS)
        
        A thin wire is wound around cylindrical spools, allowing hundreds of parallel wire segments to travel through the ingot at the same time.
        
        While the saw moves slowly through the ingot, the individual wire segments move in a translational motion, always bringing new wire into contact with silicon.
    - - After its periphery has been ground to the specified diameter, the ingot is cut into blocks of the specified length.
        
        To indicate crystal orientation, either an orientation flat or a notch is added to a portion of the peripheral.
        
        The larger primary flat - indicates crystallographic planes of high symmetry
        The second flat - indicates the type of the wafer either p/n type doped
        
        For crystals with diameter equals or larger than 200mm,no flats are ground instead a small notch is ground along the length of the ingots
  - - - Lapping is a wafer processing technique used to achieve a highly polished surface on a wafer by removing small amounts of material using a abrasive slurry.
        
        This process helps to smooth out any surface roughness and improve the flatness of the wafer, which is important for achieving high quality and uniformity in semiconductor devices.
        
        Wafers are set in a carrier, which spins between two rotating lapping plates.
        
        Both surfaces of the wafers are lapped to remove damaged surface layers and to achieve predetermined uniform thickness.
        
        The lapping process is critical in achieving high-quality wafers and is used in the manufacture of various types of semiconductor devices, including microprocessors, memory chips, and photonics components.
        
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      - Edge grind is a wafer processing step that involves grinding the outer edge of the wafer to a precise thickness and shape.
        
        This process helps to create a uniform edge profile and remove any roughness or damage caused by previous processing steps.
        
        The edge grind process is critical in ensuring that the wafer can be properly mounted and processed in later stages of the manufacturing process, as well as reducing the risk of particle contamination and mechanical damage during handling.
        
        The edge grind process typically uses a diamond grinding wheel to achieve the desired edge profile, and can be performed either before or after the lapping step, depending on the specific manufacturing process.
        
        The ingot is cut into some blocks having a specified length after its periphery is ground to the specified diameter.
        
        Either an orientation flat or a notch is added to a part of the peripheral to indicate the crystal orientation.
        
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    - - Polishing is a process used in the manufacture of semiconductor wafers to smooth the surface of the wafer and remove any imperfections. It is done after the etching process to ensure that the wafer has a smooth, uniform surface and is free of scratches, cracks, or other defects.
        
        There are several types of polishing processes, including mechanical polishing, chemical-mechanical polishing (CMP), and electro-polishing.
        
        The type of polishing process used depends on the material being polished and the desired surface finish.
        
        The goal of polishing is to achieve a high-quality surface that is suitable for further processing, such as the deposition of thin films or the formation of circuits.
        
        There are several methods used in the polishing process in making a wafer, including:
        
        Mechanical Polishing: This method involves using a rotating polishing pad with abrasive particles to physically remove material from the surface of the wafer.
        
        Chemical-Mechanical Polishing (CMP): This method combines mechanical and chemical processes to achieve a high-quality surface finish. It involves using a slurry, which is a chemical solution containing abrasive particles, to remove material from the surface of the wafer.
        
        Electro-Polishing: This method uses an electrical current to dissolve material from the surface of the wafer. The wafer is immersed in an electrolytic solution and a voltage is applied to the solution, which removes material from the surface of the wafer.
        
        The choice of method depends on the specific requirements of the polishing process and the desired surface finish.
        
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    - - Etching (chemical polishing) is a process used in the manufacture of semiconductor wafers to remove material and shape the surface of the wafer. It involves the use of a chemical solution to dissolve the material and create a pattern on the surface of the wafer.
        
        The pattern can be used to create structures such as transistors, diodes, and other components.
        
        The process is precise and controlled to ensure that the desired pattern is created and the wafer remains intact.
        
        Wafers are placed and etched in a carrier cage that rotates in an etching solution to completely remove the damaged surface resulting from the previous slicing and lapping.
        
        Acid is used for etching solution, but combination with alkaline is recently used also.
        
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  - - - Wafer are physically and chemically cleaned using ultra-pure water and chemicals.
      - "Backside Gettering" to purify silicon
    - - Wafers flatness and surface cleanliness (particle-free) are key factors as a substrate for recent leading-edge ULSI devices. Individual wafer flatness and surface particles are measured using specially designed inspection tools to assure wafer quality.
      - Wafer quality measurements :
        
        Physical dimensions, Flatness, Micro-roughness, Oxygen content, Crystal defects, Particles and Bulk resistivity
      - Measurement of Wafer Characteristics
        
        Hot Point Probe
        
        to determine whether a wafer is N or P type
        
        Two probes make ohmic contact with the wafer surface. One is heated 25-100˚C hotter than the other. A voltmeter placed across the probes will measure a potential difference whose polarity indicates whether the material is N or P type.
        
        For N-type sample: The majority carriers are electrons. At the hot probe, the thermal energy of the electrons is higher than the cold probe so the electrons will tend to diffuse away from the hot probe, driven by the temperature gradient. As the electrons diffuse away from the hot probe, they leave behind the positively charged, immobile donor atoms that provided the electrons. The negatively charged mobile electrons tend to build up near the cold probe, which results in the hot probe becoming positive with respect to the cold probe.
        
        For P-type sample: The majority carriers are holes. The polarity of the induced voltage would be reversed.
      - Measurement of Sheet Resistance
        
        Four-Point Probe
        
        most common method of measuring the wafer resistivity
        
        allow to force the current through the two outer probes and measure the voltage drop with the two inner probes using a high-impedance voltmeter.
        
        Problem with probe contacts: eliminated in the voltage measurement since no current flows through these contacts.
        
        Measurement principle (Resistivity)
        
        "Van der Pauw"
        
        uses shapes on water
      - Hall Effect Measurement
        
        determine the material type, carrier concentration and carrier mobility
        
        When current flow (from left to right), electrons flow in the opposite direction (from right to left) and the magnetic field, B is normally tangential to the current flow. When the electron moves across, they will not be evenly distributed due to the magnetic field. As a result, top and bottom will have a different potential which can be measured.
      - Fourier Transform Infrared Spectroscopy (FTIR)
        
        to measure oxygen and carbon which were introduced from CZ crystal growth process and control them
        
        measures the absorption of infrared energy by the molecules in a sample. Many molecules have vibrational modes that absorb specific wavelengths when they are excited.
        
        By sweeping the wavelength of the incident energy and detecting which wavelengths are absorbed, a characteristic signature of the molecules present is obtained.
    - - Wafers are packaged in a clean shipping case and sealed in a special moisture-proof bag.
    - - Wafers are placed in shock-absorbent shipping boxes for protection against damage caused by shock.
- - - - substrate for microelectronic devices built in
      - History
        
        These saws had diamond particles embedded into their blades to cut silicon
        
        Previously, inner diameter saws were used in the 1970s and 1980s, after conventional circular saws were employed in the 1950s and 1960s.
        
        Circular saws
        
        The early 2000s saw the introduction of multi-wire saws. Reducing material losses from the saw's kerf and enhancing the wafer's surface quality, flatness, and bow were the driving forces behind its innovation.
        
        wire saws
        
        The name "wafer" first arose in the semiconductor or silicon wafer business in the 1950s to refer to a thin, circular slice of semiconductor material, usually silicon or germanium.
        
        Single-crystal ingots are often made using the Czochralski technique, which gives them their rounded form. In the 1940s, silicon wafers were first made available.
        
        By 1960, businesses like MEMC/SunEdison started producing silicon wafers in the United States. For the first high-capacity epitaxial equipment, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley submitted Patent US3423629A in 1965 while employed by IBM.
        
        Silicon wafers are made by companies such as Sumco, Shin-Etsu Chemical, Hemlock Semiconductor Corporation and Siltronic.
        
        Jan Czochralski
        
        When he accidently dipped his pen into a crucible of molten tin instead of his inkwell in 1916, he developed the Czochralski technique. A small metal thread was dangling from the nib of his pen when he yanked it out right away. Czochralski confirmed that the metal that had crystallised was a single crystal after replacing the nib with a capillary.
      - Moore's law stated that observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years.
        
        Transistors are now three-dimensional, and the small feature size of today's advanced process technologies has required multiple exposures to reproduce these features on silicon wafers.
  - - - undergoes many microfabrication processes
        
        doping
        
        ion implantation
        
        etching
        
        thin-film deposition of various materials
        
        photolithographic patterning
      - carried out using a multi-wire saw, which simultaneously cuts several wafers from the same crystal.
        
        After that, wafers are polished to the required level of thickness and flatness.