AE07. L061KCK7
Circuits
Digital Circuits
Analog Circuits
Digital Signal
represent data
Analog Signal
high precision not needed
more values, less precision when noise is added
amplitude has continuous values
limited ranges of amplitude
Values can be still determined if affected by noise (not too high)
Not need as precise values as analog
Easy to produce million of components at large scale
Binary System: 1 and 0
interpret data
Positive logic
Negative logic
logic ranges and noise margins
store data
bit
digital words
nibble: 4 digits
byte: 8 digits
transmit data
Parallel Transmission
Serial Transmission
one wire per bit in word, plus ground wire
one bit after the other, single pair of wires
long-distance
faster, short distances
representing numerical data
1 digit
Binary Arithmetic
Addition
position
Gray Code
Subtraction
output depends only on current input
COMBINATORIAL LOGIC CIRCUIT
operate with inputs
Logic Gates
AND gate
truth table
rules
Boolean Algebra
AND
A(BC)=(AB)C
NOT gate
higher amplitude:1; lower amplitude:0
higher amplitude:0; lower amplitude:1
numbers
Binary form
Hexadecimal-Binary Conversion
Binary-Coded Decimal Format (BCD)
OR gate
truth table
OR
A(B + C) = AB + AC
A + 0 = A
A + 1 = 1
A + A = A
truth table
NOT
A0=0
A1=1
(A + B) + C = A + (B + C) = A + B + C
De Morgan's Law
way to remember
Invert variables, switch places between AND and OR, invert entire expression = same as before
grouping / ungrouping
Octal-Binary Conversion
grouping / ungrouping
Binary-Decimal Conversion
Multiplication
Division
Two's Complement form
8421 BCD
4221 BCD
since the maximum digit is 9=4+2+2+1
maximizing speed, free from errors
Binary Code
erroneous positions during transition if digits don't change simultaneously
in theory
in practice
only one line needs to change (used in Karnaugh maps)
start with line of zeros, change the lsb to a new state
do not confuse with Binary Arithmetic
1: true 0: false
"the bar of the sum is the product of the bars",
'the bar of the product is the sum of the bars"
truth table
high output only if both inputs have same value
to apply logic signal to low-impedance load
implement logic circuits
minimize logic circuits
only one type of operation
NAND
AND from NAND
NOT from NAND
OR from NAND
SOP Implementation
POS Implementation
stored in computer, useful for calculations
division (multiplication for decimal part) / weighted sum
sum of minterms corresponding to a line of the truth table for which the output is 1
product of maxterms corresponding to a line of the truth table for which the output is 0.
Karnaugh Maps
Borrow to compute
Carry to compute
output depends on both present and past input
SEQUENTIAL LOGIC CIRCUITS
building block
have memory
Flip-Flops
Simple Flip Flop
two stable states possible
not useful, can't control states
Set-Reset Flip-Flop (SR FF)
Clocked SR FF
can control states
used to debounce a switch
Clocked SR FF with Asynchronous Inputs
can also control moment that FF responds to inputs
clock signal must be high to enable R and S signals as inputs of the SR FF
with R and S low, the SR FF "remembers" which input (R or S) was high most recently
Edge-Triggered D Flip-Flop
can also set or clear FF independently of clock
if preset input is high, Q becomes high; if clear input is high, Q becomes low
if S is high and R low, Q is high ; if R is high and S low, Q is low
responds to inputs only at a transition in the clock signal
respond when clock switches from low to high (leading edge)
respond when clock switches from high to low (trailing edge)
Positive-edge-triggered circuits
Negative-edge-triggered circuits
D Flip-Flop
JK Flip-Flop
delays data D from reaching output one clock pulse
SR FF in which S and R are complement
Interconnecting flip-flops
Registers
Counter
Parallel-In Serial-Out Shift Register
Serial-In Parallel-Out Shift Register
Octal
Hexadecimal
BCD
AB=BA
Logic gates can be interconnected to form flip-flops. Interconnections of flip-flops form registers. A complex digital system, such as a computer, consists of many gates, flip-flops, and registers. Thus, logic gates are the basic building blocks for complex digital systems
similar to SR FF, except that if the J and K inputs are both high, the output toggles on the next trailing edge