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AE07. L061KCK7, representing numerical data, Circuits, represent data -…

- - - - Logic Gates
        
        AND gate
        
        truth table
        
        rules
        
        Boolean Algebra
        
        AND
        
        A(BC)=(AB)C
        
        A0=0
        
        A1=1
        
        AB=BA
        
        OR
        
        A(B + C) = AB + AC
        
        A + 0 = A
        
        A + 1 = 1
        
        A + A = A
        
        (A + B) + C = A + (B + C) = A + B + C
        
        NOT
        
        De Morgan's Law
        
        way to remember
        
        Invert variables, switch places between AND and OR, invert entire expression = same as before
        
        "the bar of the sum is the product of the bars",
        'the bar of the product is the sum of the bars"
        
        do not confuse with Binary Arithmetic
        
        NOT gate
        
        truth table
        
        OR gate
        
        truth table
        
        1: true 0: false
        
        truth table
        
        to apply logic signal to low-impedance load
        
        high output only if both inputs have same value
    - - minimize logic circuits
        
        only one type of operation
        
        NAND
        
        AND from NAND
        
        NOT from NAND
        
        OR from NAND
        
        Karnaugh Maps
      - SOP Implementation
        
        sum of minterms corresponding to a line of the truth table for which the output is 1
      - POS Implementation
        
        product of maxterms corresponding to a line of the truth table for which the output is 0.
- - - - Flip-Flops
        
        Simple Flip Flop
        
        two stable states possible
        
        not useful, can't control states
        
        Set-Reset Flip-Flop (SR FF)
        
        can control states
        
        used to debounce a switch
        
        with R and S low, the SR FF "remembers" which input (R or S) was high most recently
        
        if S is high and R low, Q is high ; if R is high and S low, Q is low
        
        Clocked SR FF
        
        Clocked SR FF with Asynchronous Inputs
        
        Edge-Triggered D Flip-Flop
        
        1 more item...
        
        4 more items...
        
        can also control moment that FF responds to inputs
        
        clock signal must be high to enable R and S signals as inputs of the SR FF
        
        Interconnecting flip-flops
        
        Registers
        
        Parallel-In Serial-Out Shift Register
        
        Serial-In Parallel-Out Shift Register
        
        Counter
- - - - Carry to compute
  - - - Borrow to compute
- - - - only one line needs to change (used in Karnaugh maps)
  - - - in theory
        
        in practice
- - - - grouping / ungrouping
    - - grouping / ungrouping
    - - division (multiplication for decimal part) / weighted sum
  - - - since the maximum digit is 9=4+2+2+1
- - - - high precision not needed
        
        logic ranges and noise margins
- - - - more values, less precision when noise is added
- - - - higher amplitude:1; lower amplitude:0
    - - higher amplitude:0; lower amplitude:1
  - - - digital words
        
        nibble: 4 digits
        
        byte: 8 digits
      - 1 digit
  - - - one wire per bit in word, plus ground wire
      - faster, short distances
    - - one bit after the other, single pair of wires
      - long-distance