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DFX (Design for X) - Coggle Diagram
DFX (Design for X)
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DFB (Design For Debug)
- Debug is to root cause issues and unexpected behaviors, so all products features must be verified at post-silicon.
- Previously, debug was done on specially build board and setup on the hardware equipment, but it is costly, time consuming and high risk to cause another hardware issues.
- DFD will reduce these risks and debug now is done on the system without open the cover for debug.
- Generally, debug involves the power up/ boot sequence, low power debug, OS/drivers/Apps.
- Debug components: JTAG, VISA, DCI, NPK, CrashLog
JTAG
- Standard interface for Boundary Scan (Bscan)
- 5 pins: TCK, TDI, TMS, TDO, TRSTB
- TAP Control (Test Access Port): predefined Bscan instructions
- Allow multiple TAP control on single JTAG
TAP
- primary test and debug access mechanism
- TAP Controller State Machine (IEEE 1149.1):
16 stage with 4 major operations: Reset, Run-Test, Scan-DR, Scan-IR
Scan: Capture, Shift, Update
VISA
- primary way to observe internal signal at pin level
- divided into 3 segments mux: Unit LM, Partition LM, Center LM
- output: pin Northpeak (Mem, pin, DCI)
- Design consists of many partition blocks and contains the signal that we want to observe.
- Each signal is connected to configurable muxs and the mux output connect to partition-level mux.
- The partition-mux then connected to central mux, which itself connected to observe endpoint.
- Selectors controlled by registers, which writing the signal to reg allows selected observed signal to the end point.
DCI (Direct Connect Interface)
- Closed Chassis Debug (using external adapter to debug).
- Debug adapter connected in between host and debug target.
- Once connected, target will send the interface, register, pins information to the debug host.
NPK (North Peak)
- set of silicon features, target system API used for debug tools and software stack
- Enable: System-level Debug, HW & SW co-debug, third party vendors to create debug tools, architectural product-to-product consistency
DFT (Design For Test)
- one of the features in PCH to ensure high effective defect screening strategy for the entire PCH.
- save cost, time and efficient test methodology and power. DFT in PCH is the way to ensure the quality of the devices.
- Basically, DFX components consists of structural and functional modes to cater different mode of testing.
- DFT (Test): HVM testability, platform testability
- DFT (Validation): SV, DV, EV, MV
- DTF (Survivability): A0 Debug Strap,/ Debug & Override Registers
- DFT (Modularity): Chassis, SIIP
MBIST
- Support self-test flow and functional safety
- IJTAG network
- Memory BIST: on-die logic to test memory array for defects.
- build in logic to generate pattern and compare at speed. Control via TAP
STF/SCAN
Goal: improve controllability and observability of internal flip-flop/ detects defects in the combinational logic
connect virtually all flip-flop in chains by converting each flip-flop into mux-flop structure
- SCAN uses SCANUNIT architecture
- Structural Test Fabric (STF)
- Parallel SCC and Parallel SRC Controllers
STF (Structural Test Fabric)
- Load/Unload
- Capture
- Scan test sequence
TAM
- 16 bits input data through GPIO with 1 clock, 1 command.
- Supports IOSF primary access to any IP to transport test vectors.
- Sideband access through P2SB.
- TAM can be accessed through IOSF or SM (for preloaded test execution).
- Enable IP test to be converted into HVM test
- multiple root spcae
- HSIO loopback
- FW pre-load into SRAM
- FUSA (fabric parity end to end check)
FUSA
- Consists of fuse controller (1 per die) and fuse puller (1 per IP).
- At reset fuse controller sense all fuse and store in RAM or RF.
- When IP's fuse puller request fuse via IOSF-SB, fuse controller return fuse data through LUT
- If no fuse data returned, reset value is default fuse value.
Boundary Scan
- Full IO coverage except critical PM pins
- HVM coverage for all IOs
- Interconnect test for board testing
Usage - DC Tests for Digital Circuits
- Functional boot requirement
- non-standardized way of power up requirement for 14nm HIP
- Multiple SOC plumbing needed to simplify PHY boot for bscan.