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Wafer Fab ?s - Coggle Diagram

- - - - This how I did it
      - I encountered a couple difficulties along the way
        
        This is how I resolved
        
        This is how I motivated people in other groups to obtain help I needed
    - - I used JMP, spotfire, Minitab, etc.
      - I did full factorial
      - I did DOE
      - I performed T-test
    - - I set up the equipment
      - I did the leakage tests
    - - checklist
      - troubleshoot
      - Result: now that we implemented change it reduced cycle time by 20% etc.
- - - - reach out to SMEs
    - - work with them to improve yield
      - Explain why it's necessary
- - - - what's each region do?
      - what's it used for?
  - - - depletion mode
      - enhancement mode
    - - what does the name mean?
      - how does it work v. a MOSFET?
- - - - components I qual must meet
  - - - requirements
        
        electrical, mechanical, temperature, etc.
        
        What tests really stress the component approriately
        
        Qual, Characterization,
        Reliability Demonstration
        
        "flow up"
        
        HTGB
        
        TC
        
        HRTB
- - - - DFSS, 5S, 8D, 5Y DOEs, Failure Analysis, ANOVA test, t-test
      - once understood how to turn/off >> created model
    - - monitored change for x time period & y improvement
  - - - DMAIC