CPU STRUCTURE AND FUNCTION - Coggle Diagram
CPU STRUCTURE AND FUNCTION
THE x86 PROCESSOR FAMILY
Generated from software & is provoked by the execution of an instruction.
-INTERRUPT VECTOR TABLE-
Every type of interrupt is assigned a number. Number is used to index into the interrupt vector table.
Generated by a single from hardware & it may occur at random times during the execution of a program
THE ARM PROCESSOR
Have full access to system resource and can change modes freely. Contain
Supervisor mode, Abort mode, Undefined Mode, Fast interrupt Mode, Interrupt Mode
ARM Architecture supports seven execution modes. Most application programs execute in user mode. The OS can tailor the use of system software to a variety of circumstances.
Occur when the pipeline or some portion of the pipeline, must stall because conditions does not permit continued execution. There are 3 types of hazards :
( Resource, Data, Control )
Dealing With Branches
Similar to the use of an assembly line in a manufacturing plant. To apply this concept to instruction execution we must recognize that an instruction has a number of stages.
Intel 80486 Pipelining
-DECODE STAGE 1-
All opcode and addressing-mode information is decode in the D1 stage. 3 bytes of instructions are passed to the D1 stage from the prefetch buffers. D1 decoder can then direct the D2 stage to capture the rest of the instruction.
-DECODE STAGE 2-
Expands each opcode into control signals for the ALU. Also control the computation of the more complex addressing modes.
Stage include ALU operations, cache access and register update.
Updates registers and status flags modified during the preceding execute stage.
Objective to fill the prefetch buffers with new data as soon as the old data have been consumed by the instruction decoder. Operates independently of the other stage to keep the prefetch buffers full.
Control & Status Register
Used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs.
Enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.
The execution on an instruction may require reading data from memory or an I/O module.
The execution of on instruction may require performing some arithmetic or logical operation on data.
The instruction is decode to determine what action is required.
The result of the execution may require writing data to memory or an I/O module.
The processor reads an instruction from memory (register, cache, main memory)
Interpret the opcode and perform the indicate operation.
If interrupt is enabled and an interrupt has occurred, save the current process state and service the interrupt
Read the next instruction from memory into processor