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CPU Structure & Function - Coggle Diagram
CPU Structure & Function
:warning: Instruction Pipelining
Pipelining Strategy
Similar to the use of an assembly line in a manufacturing plant.
New inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.
To apply this concept to instruction execution we must recognize that an instruction has a no. of stages.
Additional Stages
Fetch Instruction (FI)
Decode Instruction (DI)
Calculate Operands (CO)
Fetch Operands
(FO)
Execute Instruction (EI)
Write Operand (WO)
Pipeline Hazards
Occur when the pipeline, or some portion of the pipeline, must stall because conditions do not permit continued execution.
Also referred to as pipeline bubble.
There are 3 types of hazards :
--> Resource
--> Data
--> Control
Dealing Branches
Multiple streams
Prefetch brand target
Loop buffer
Branch prediction
Intel 80486 Pipelining
Fetch -> Decode stage 1 -> Decode stage 2 -> Execute -> Write back
:warning: Processor Organization
Fetch Instruction
The processor reads an instruction from memory (register, cache and main memory)
Interpret Instruction
The instruction is decoded to determine what action is required.
Fetch Data
The execution of an instruction may require reading data from memory or an I/O module.
Process Data
The execution of an instruction may require performing some arithmetic or logical operation on data.
Write Data
The result of an execution may require writing data to memory or an I/O module.
:warning: Register Organization
User-Visible Registers
Enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.
Control & Status Register
Used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs.
:warning: Instruction Cycle
Includes the following stages :
Fetch
Read the next instruction from the memory into the processor.
Execute
Interpret the opcode and perform the indicated operation.
Interrupt
If interrupts are enabled and an interrupt has occurred, save the current process state and service the interrupt.
:warning: The x86 Processor Family
Register Organization
Interrupt Processing
Interrupts
--> Generated by a signal from hardware and it may occur at random times during the execution of a program.
--> Maskable
--> Non-maskable
Exception
--> Generated from software and is provoked by the execution of an instruction.
--> Processor detected - processor encounters an error.
--> Programmed - instruction that generate an exception.
Interrupt vector table
--> Every type of interrupt is assigned a number.
--> Number is used to index into the interrupt vector table.
:warning: The ARM Processor
ARM architecture supports seven execution modes.
Most application programs execute in user mode.
Remaining six execution modes are referred to as privileged mode.
