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NM2 Test System -- System Requirements - Coggle Diagram
NM2 Test System -- System Requirements
RM -- Mechanical Requirements
RM1
-- The Physical Test System (PTS) shall fit into the SEE test chamber
RM1.2
-- The PTS width shall be between 10cm and 15cm.
RM1.3
-- The PTS length shall be between 10cm and 15cm.
RM1.1
-- The PTS height shall be between 5cm and 10cm.
RM1.4
-- The PTS should host between 2 and 4 DuTs.
RM1.5
-- The PTS should use the same dimensions as Galeo test cards.
RM.MB -- Module Board Requirements
RM.MB2
-- The CoB version shall accommodate a metal lid.
RM.MB2.2
-- The metal lid length shall be between 2cm and 4cm.
RM.MB2.3
-- The metal lid height shall be less than 1cm.
RM.MB2.4
-- An existing metal lid should be reused.
RM.MB2.1
-- The metal lid width shall be between 2cm and 4cm.
RM.MB3
-- The CoB version shall include a heating element directly below the DuT.
RM.MB3.1
The difference in thermal resistivity from the heating element to the DuT and to the temperature sensor shall be less than 2K/W.
RM.MB4
-- The DuT shall be placed face-up on the MB.
RM.MB1
-- The MB shall be fabricated in two versions -- A and B.
RM.MB1.1
--Version A (CoB) shall mount the DuT as a Chip-on-board.
RM.MB1.2
-- Version B (CQFP) shall mount the DuT in a CQFP package.
RM.MB1.3
-- Both versions shall be interchangeable.
RM.MB5
-- The MB shall be mounted on the TC.
RM.MB5.1
The MB shall be detachable.
RM2
-- The PTS shall include a Test Card (TC) PCB.
RM2.1
-- The TC shall contain six 3.4mm mounting holes.
RM3
-- The PTS shall include a Module Board (MB) PCB.
RM3.1
-- The Module board shall contain two 3.4mm mounting holes.
RSA -- System Architecture Requirements
RSA1
-- The System Architecture (SA) shall include the Device under Test (DuT).
RSA1.1
-- The NIRCA MKII ASIC shall be the DuT.
RSA2
-- The SA shall include the Analogue Module (AM).
RSA2.1
-- The AM shall contain current bias generation.
RSA2.2
-- The AM shall contain voltage reference generation.
RSA2.3
-- The AM shall contain filters.
RSA2.4
-- The AM shall contain temperature sensors.
RSA2.5
-- The AM shall contain current sensing resistors.
RSA2.6
-- The AM shall contain heating elements.
RSA2.7
-- The AM shall contain the ODAC Load Module (OLM).
RSA3
-- The SA shall include the Control Module (CM).
RSA3.1
-- The CM shall contain the Data Capturing Module (DCM).
RSA3.2
-- The CM shall contain the Configuration Module (CgM).
RSA3.3
-- The CM shall contain the memory.
RSA3.4
-- The CM shall contain the clock generation.
RSA4
-- The SA shall include the Power Distribution Module (PDM).
RSA5
-- The SA shall include the External Interface (XIF).
RSA6
-- The SA shall include the Internal Interface (IIF).
RSA7
-- The SA shall include an FPGA module (FPGAM).
RSA7.1
-- The FPGA module shall be the Trenz module TE0720 or pin-compatible variation.
RE -- Electrical Requirements
RE1
-- The PTS shall include all external components necessary for operating the DuT.
RE.MB -- Module Board Requirements
RE.IIF -- Internal Interface Requirements
RE.IIF1
-- The MB shall include board-to-board (B2B) connectors with at least 200 pins.
RE.IIF2
-- The MB shall include the
Monitor1_nomount
Standardised Interface Connection (SIC).
RE.IIF2.2
-- The
Monitor1_nomount
SIC shall include a DNM ≤0603 shunt capacitor.
RE.IIF2.3
-- The
Monitor1_nomount
SIC shall include a DNM ≤0603 series resistor.
RE.IIF2.1
-- The
Monitor1_nomount
SIC shall physically interface between a DuT pin and a B2B connector.
RE.IIF2.4
-- DuT pins
VADC_SREFP, VADC_SREFN, test1, REXT, VADC_SREFP
and
VADC_SREFN
shall use the
Monitor1_nomount
SIC.
RE.IIF3
-- The MB shall include the
Monitor2_nomount
SIC.
RE.IIF3.1
-- The
Monitor2_nomount
SIC shall physically interface between a DuT pin and a B2B connector.
RE.IIF3.2
-- The
Monitor2_nomount
SIC shall include a DNM ≤0603 shunt capacitor.
RE.IIF3.3
-- The
Monitor2_nomount
SIC shall include a DNM shunt ≤2.54mm jumper.
RE.IF3.4
-- The
Monitor2_nomount
SIC shall include a DNM ≤0603 series resistor.
RE.IIF3.5
-- DuT pins
ADC_REFP, ADC_REFN
and
ADC_REFCM
shall use the
Monitor2_nomount
SIC.
RE.IIF4
-- The MB shall include the
Monitor3_nomount
SIC.
RE.IIF4.1
-- The
Monitor3_nomount
SIC shall physically interface between differential DuT pins and a B2B connector.
RE.IIF4.2
-- The
Monitor3_nomount
SIC shall include a 200nF ≤0603 shunt capacitor.
RE.IIF4.3
-- The
Monitor3_nomount
SIC shall include a DNM 3-pin shunt ≤2.54mm jumper to gnd.
RE.IF4.4
-- The
Monitor3_nomount
SIC shall include a pair of DNM ≤0603 series resistors.
RE4.5
-- DuT pins
VREFP
and
VREFN
shall use the
Monitor2_nomount
SIC.
RE.IIF5
-- The MB shall include the
Monitor1_nomount_bgr
SIC.
RE.IIF5.1
-- The
Monitor1_nomount_bgr
SIC shall physically interface between a DuT pin and a B2B connector.
RE.IIF5.2
-- The
Monitor1_nomount_bgr
SIC shall include a 10uF ≤0603 shunt capacitor.
RE.IIF5.3
-- The
Monitor1_nomount_bgr
SIC shall include a DNM ≤0603 series resistor.
RE.IIF5.4
-- DuT pin
BGR_VREF
shall use the
Monitor1_nomount_bgr
SIC.
RE.IIF6
-- The MB shall include the
ODACout2
SIC.
RE.IIF6.1
-- The
ODACout2
SIC shall physically interface ODAC and ODAC_SENSE pins and a B2B connector.
RE.IIF6.2
-- The
ODACout2
SIC shall include a 100nF ≤0603 shunt capacitor to ground on DuT ODAC pins.
RE.IF6.3
-- The
ODACout2
SIC shall include a 0 ohm ≤0603 series resistor on DuT ODAC_SENSE pins.
RE.IIF6.4
-- The
ODACout2
SIC shall include a ≤2.54mm jumper from DuT ODAC to ODAC_SENSE pins.
RE.IIF6.5
DuT pins
ODAC7
and
ODAC7_SENSE
shall use the
ODACout2
SIC.
RE.IIF7
-- The MB shall support the physical LVDS data link.
RE.IIF7.5
-- A ≤5% 100 ohm resistor with maximum 3nH ESL shall terminate the LVDS receiver pins.
RE.IIF7.4
-- A ≤5% 100 ohm resistor with maximum 6nH ESL shall terminate the LVDS Driver pins.
RE.IIF7.1
-- The physical LVDS link shall interface between
TX
and
TX_CLK
differential pins and a B2B connector.
RE.IIF7.2
-- The physical LVDS link shall observe 50 ohm characteristic impedance.
RE.IIF7.3
-- The physical LVDS link should have trace-to-trace spacing of ≤1 trace width.
RE.IIF8
-- The MB shall interface external power supplies through the B2B connectors.
RE.IIF9.1
The MB shall interface with the 3.3V
AVDD3V3
voltage supply delivering up to 1.7W of power.
RE.IIF9.2
The MB shall interface with the 3.3V
AVDD3V3_REF
voltage supply delivering up to 3.2W of power.
RE.IIF9.3
-- The MB shall interface with the 3.3V
DVDD3V3
voltage supply delivering up to 360mW of power.
RE.IIF9.4
The MB shall interface with the 1.8V
DVDD1V8
voltage supply delivering up to 1050mW of power.
RE.AM -- Analog Module Requirements
RE.AM1
-- The MB shall include a Pt100 element placed within a 2cm radius of the DuT.
RE.AM2
-- The MB shall include external biasing resistors.
RE.AM2.1
-- A ≤1% 10 kohm resistor shall bias the DuT REXT pin.
RE.AM2.2
-- A ≤5% 6.8 kohm resistor shall bias the
RREF
LVDS pin.
RE.AM2.2.1
-- The
RREF
LVDS pin shall have ≤40pF parasitic capacitance.
RE.PDM -- Power Distribution Module Requirments
RE.PDM1
-- The MB shall include the Power Distribution Network (PDN) for the
AVDD3V3
voltage supply.
RE.PDM1.1
-- The
AVDD3V3
impedance profile shall be ≤250 mohm up to 80MHz.
RE.PDM2
-- The MB shall include the PDN for the
AVDD3V3_REF
voltage supply.
RE.PDM2.1
-- The
AVDD3V3_REF
impedance profile shall be ≤250 mohm up to 10MHz.
RE.PDM3
-- The MB shall include the PDN for the
DVDD3V3
voltage supply.
RE.PDM3.1
-- The
DVDD3V3
impedance profile shall be ≤3 ohm up to 50MHz.
RE.PDM4
-- The MB shall include the PDN for the
DVDD1V8
voltage supply.
RE.PDM4.1
-- The
DVDD1V8
impedance profile shall be ≤350 mohm up to 240MHz.
RE.MB1
-- The MB shall only contain passive components, excluding the DuT.
RE.XIF -- External Interface Requirements
RE.XIF1
-- The MB shall include ≥1 mm diameter test points.
RE.XIF1.1
-- The DuT pin
test3
shall be routed to a test point.
RE.TC -- Test Card Requirements
RE.CM -- Control Module Requirements
RE.DCM -- Data Capturing Module Requirements
RE.DCM1
-- The TC shall receive (RX) data from the Serial Data Interface (TX).
RE.DCM1.1
-- The TC shall be compatible with the proprietary packet protocol.
RE.DCM1.1.1
The TC shall receive 8/10b encoded data.
RE.DCM1.2
-- The TC shall receive (RX) 9 dedicated ≤480Mbps DDR LVDS Serial Data channels.
RE.DCM1.3
-- The TC shall receive (RX_CLK) 1 dedicated ≤240MHz LVDS clock channel.
RE.DCM1.4
-- The TC shall detect and store all link and CRC errors.
RE.DCM1.5
-- The TC shall terminate 100ohm LVDS at the receiver.
RE.DCM1.6
-- The TC should equalize RX signals.
RE.DCM2
-- The TC shall be capable of through-putting data at ≤3.84Gbps from the DuT via an industry-standard data link to the XIF.
RE.DCM3
-- The TC shall use a total trace length of ≤17.5cm for each individual LVDS signal.
RE.CgM -- Configuration Module
RE.CgM1
-- The TC shall support communication over 4-wire SPI.
RE.CgM2
-- The TC shall support communication over the Sensor Control I/O.
RE.CgM2.1
-- The TC shall receive data on 16
DOUT
channels at ≤24Mbps.
RE.CgM2.2
-- The TC shall transmit data on 8
DIN
channels at ≤24Mbps.
RE.CgM2.3
-- The TC shall transmit serial data on 1
DIN_SERIAL
channel at ≤24Mbps.
RE.CgM2.4
-- The TC shall receive/transmit 8b serial data.
RE.CgM2.3.1
-- The serial data shall support different polarities.
RE.CgM2.3.2
-- The serial data shall support MSB/LSB first settings.
RE.CgM3
-- The TC shall generate a trigger pulse to the
ACQ
pin.
RE.CgM3.1
-- The pulse length should be programmable starting at ≥20ns.
RE.CgM4
-- The TC shall support the DFT scan chain.
RE.CgM4.1
-- The DFT scan channels shall support ≤100kbps data rates.
RE.CgM5
-- The TC shall receive IRQ flags.
RE.CgM6
-- The TC shall generate interrupts for the programmable interrupt pins PIRQ1 and PIRQ2.
RE.CgM7
-- The TC shall generate the DuT system reset signal
RESET_N
.
RE.CM1
-- The TC shall generate SYS_CLK_P/N.
RE.CM1.1
-- The SYS_CLK_P/N shall support 15MHz LVDS clocking.
RE.CM1.2
-- The SYS_CLK_P/N shall support 240MHz LVDS clocking.
RE.CM1.3
-- The phase noise should be ≤ 2ps.
RE.CM2
-- The TC shall generate a 20 MHz SPI Clock.
RE.XIF -- External Interface Requirements
RE.XIF2
-- The TC shall support external data communication over Ethernet.
RE.XIF3
-- The TC shall support external HS data transfer of ≤3.84Gbps using an industry standard.
RE.XIF4
-- The TC shall include ≥1mm diameter test points.
RE.XIF4.1
-- At least one test-point shall be present on signals
DOUT0-15
.
RE.XIF5
-- The TC shall include 2.54mm headers.
RE.XIF5.1
-- At least one header pin shall access signals DIN0-7.
RE.XIF5.2
-- At least one header pin shall access signal DSERIAL_IN.
RE.XIF6
-- The TC shall include SMA connectors.
RE.XIF6.1
-- At least one SMA connector shall access pseudo-differential signals AIN0-15.
RE.XIF6.2
-- At least one SMA connector shall access signals AUX0-2 and AUX_INM.
RE.XIF7
-- The TC shall include Mini-Fit Jr. connectors.
RE.XIF7.1
-- The Mini-Fit Jr. connectors shall supply 5V.
RE.XIF7.2
-- One Mini-Fit Jr. connector shall access each power domain
AVDD3V3, AVDD3V3_REF, DVDD3V3
and
DVDD1V8
.
RE.PDM -- Power Distribution Module Requirements
RE.PDM5
-- The TC system power (
VSYS5V0
) shall be 5V DC.
RE.PDM5.1
-- The TC system power shall generate power domains
AVDD3V3, AVDD3V3_REF, DVDD3V3, DVDD2V5
and
DVDD1V8
.
RE.PDM5.2
-- A load current of ≤4A shall be supported by the system power.
RE.PDM6
-- The TC shall include Voltage Regulator Modules (VRMs).
RE.PDM6.1
-- The VRMs shall regulate the
AVDD3V3
power domain.
RE.PDM6.1.2
-- Total voltage root-mean-squared (Vrms) noise and distortion on the
AVDD3V3
power domain shall not exceed 3% of its DC-value.
RE.PDM6.1.1
-- A load current of ≤500mA shall be supported by the
AVDD3V3
VRM.
RE.PDM6.7
-- The VRMs shall regulate external accessible references
BGR_VREF, VREF, ADC_REF
and
SREF
.
RE.PDM6.2
-- The VRMs shall regulate the
AVDD3V3_REF
power domain.
RE.PDM6.2.1
-- A load current of ≤860mA shall be supported by the
AVDD3V3_REF
VRM.
RE.PDM6.2.2
-- Total voltage root-mean-squared (Vrms) noise and distortion on the
AVDD3V3_REF
power domain shall not exceed 3% of its DC-value.
RE.PDM6.3
-- The VRMs shall regulate the
DVDD3V3
power domain.
RE.PDM6.3.2
-- Total voltage root-mean-squared (Vrms) noise and distortion on the
DVDD3V3
power domain shall not exceed 5% of its DC-value.
RE.PDM6.3.1
-- A load current of ≤100mA shall be supported by the
DVDD3V3
VRM.
RE.PDM6.5
-- The VRMs shall regulate the
DVDD25
power domain.
RE.PDM6.5.2
-- Total voltage root-mean-squared (Vrms) noise and distortion on the
DVDD25
power domain shall not exceed 5% of its DC-value.
RE.PDM6.5.1
-- A load current of ≤1.5A shall be supported by the
DVDD25
VRM.
RE.PDM6.6
-- The VRMs shall regulate the
DVDD1V8
power domain.
RE.PDM6.6.2
-- Total voltage root-mean-squared (Vrms) noise and distortion on the
DVDD1V8
power domain shall not exceed 5% of its DC-value.
RE.PDM6.5.1
-- A load current of ≤550mA shall be supported by the
DVDD1V8
VRM.
RE.PDM6.4
-- The VRMs shall regulate the
DVDD33
power domain.
RE.PDM6.4.1
-- A load current of ≤3A shall be supported by the
DVDD33
VRM.
RE.PDM6.4.2
-- Total voltage root-mean-squared (Vrms) noise and distortion on the
DVDD33
power domain shall not exceed 5% of its DC-value.
RE.PDM7
-- The TC shall include series sense resistors on power nets.
RE.PDM7.1
-- The series sense resistors shall be present on power nets
VSYS5V0, AVDD3V3, AVDD3V3_REF, DVDD3V3
and
DVDD1V8
.
RE.AM -- Analog Module Requirements