Computer systems orgization, PIOA/C enable: PMC_PCER0 bit 11/13, Lec 8,…
Computer systems orgization
"Special subroutines used to interract with harware"
Takes 100% of CPU
Difficult to handle multiple diffrent events
Iterrupt handler = Automatically called subroutine
Exception e.g. try to divide by 0
Hardware interrupt e.g. button pressd
Software interrupt e.g. call to operating system
"ARM decided to call everything exception,
whereas, Intel calls everything Interrupt. "
Sometimes, a simpler classification into internal
(CPU-generated) and external (hardwaregenerated) interrupts is used.
Maskable e.g. Systick
2 things are requiered: Interrupt Source, interrupt handler
Interrupts with a handler not fixed at a specific point in memory e.g. SystickHandler
Non-Vectored interrupts, the oposite of vectored interrupts
Interrupt priority e.g. (CPU temp = 150°C) > button pressed
Interrupt vector table
after power on, adress: 0x0000000
first value: Stack pointer
second value: Reset Handler
Move vector table adress using VTOR
startup_sam3x.s Contains a full vector table with each handler
Checks if an exception has occured after every process
Why does the CPU save PSR?
It saves the flags
FAULTMASK: Enable or dissable all exceptions exept: Hard Fault Non-Maskable interrupts or interrupts
PRIMASK enable or dissable all exceptions except for: Hard Fault or NMI
BASEPRI contains masking priority levels, acessed through MRS (read) and MSR (write)
Nested Vectored Interrupt Controller (NVIC)
Can turn on/of vectored interrupts induvidually
to mask a interrupt use corresponding CLRENA bit (ICER)
To unmask a interrupt use the corresponding SETENA bit in the NVIC (ISER)
To set an interrupt to "pending" use SETPEND or CLRPEND
How to configure exception/interrupt
Parallel IO controllers (PIO)
Nibble = 4-Bit
Byte = 8-Bit
half-Word = 16-Bit
Word = 32-Bit
Double-Word = 64-Bit
If the negative ﬂag is updated, it is set if the instruction resulted in a negative value, otherwise it is reset. In practice, this ﬂag contains the most signiﬁcant bit of the result.
If the zero ﬂag is updated, it is set
if the instruction resulted in a zero value, otherwise it is reset..
ﬂag is set if it has the value 1. It is reset if it has the value 0
CARRY (C) FLAG
The carry flag is set if the addition of two numbers causes a carry out of the most significant (leftmost) bits added. 1111 + 0001 = 0000 (carry flag is turned on)
ﬂag is set if it has the value 1. It is reset if it has the value 0.
OVERFLOW (V) FLAG
In computer processors, the overflow flag (sometime called V flag) is usually a single bit in a system status register used to indicate when an arithmetic overflow has occurred in an operation, indicating that the signed two's-complement result would not fit in the number of bits used for the operation.
The carry ﬂag is used for unsigned operations, while the overﬂow ﬂag is used for signed operations.
Watchdog Timer (WDT) [L:8,S:16]
prevents: System lock-up
Mode: WDT_MR (disable)
Power Management Controller (PMC)
CK enable 0: PMC_PCER0
CK dissable 0: PMC_PCDR0
CK status 0 : PMC_PCSR0
General Purpose IO (GPIO)
a pin on a chip, controllable by software.
Grouped an these groups are called ports
103 of all 144 pins on SAM3X SoC are GPIO
Often have multiple functions
Parallel IO controllers (PIO)
One PIO for each port (up to 32 bit)
For each Pin on a PIO, three functions can be selected
Multidriver Status: PIOA_MDSR
Pull-up status: POIA_PUSR
Output data status: PIOA_ODSR
Declare output: PIOA_OER
Enable PIO: PIOA_PER
Make high: PIOA_SODR
Make low: PIOA_CODR
THE SUFFIX "S"
• Resetting (Clearing) bits : assigning a certain bit or bits to 0.
• Assigning bits : assigning a certain bit or bits to specific value.
• Setting bits : assigning a certain bit or bits to 1.
• Reading bits : reading a certain bit or bits.
• Testing bit : whether a certain Bit equal to 1 or 0.
Load-Store Instructions transfer data between registers and memory
• Multiple-Register Transfers (LDM, STM)
• Single-Register Transfer
• Big Endian: address of most significant byte = word address (xx00 = Big End of word)
• Little Endian: address of least significant byte = word address (00xx) = Little End of word)
Pre-index and Post-index
• We want to be able to change the program flow depending on the data values or what happened during an arithmetic operation (e.g. overflow).
• By changing the Program Counter (PC) address value we can execute any part of our program in the order we want and thus change the program flow.
Jump(Changes value of the PC)
Branch (Jump) Instructions
• Processors normally support subroutines, usually in the form of special registers or via stack instructions.
• If a subroutine has values, we usually call them functions while if they do not return anything we call them procedures .
• A subroutine takes one or more values (arguments) and generates one or multiple values (results or return values)
• Two registers that are reserved for subroutines: •R13 is a so-called Stack Pointer (SP)
• R14 is a Link Register (LR)
Often you want a subroutine to be able to call other subroutines (nested subroutines).
A Stack is a form of storage space in memory that is defined by what you add Last is what you can pick out First.
The mechanism that the last thing you add is the first thing you take away is called Last In First Out (LIFO) .
A stack is an abstract data type, defined by which operations you can do on it and not how it really is constructed.
PUSH and POP
Most instructions in a program appear to be executed sequentially, even if the underlying hardware does not actually execute them in order
Loops provide a way to repeat a set of instructions, and appear in diﬀerent kinds. A single while-loop is enough to implement any loop structure. Some loops types (for) have a predetermined number of iterations, other loops run while some speciﬁc condition is (while, do..while) or becomes (repeat..until) true. Often, programming languages provide a way to change the normal control ﬂow inside a loop (break, continue).
Selections select one set of statements depending on some conditions. A single if-statement is enough to implement any selection structure, but more powerful structures (if/else if, switch) are very helpful.
System timer: Systick
Reloads (Wrap around back to load value)
Does not count when halted
Bit : 0 - Enable, 1- Tickint, 2- CLK_SRC, 16: COUNTFLAG
Uses processor clock
Not based on CPU
32 bit up counter
clocked from SCK (divided by 16 bit prescalar)
can generate interrupt every tick
can generate interrupt at programable alarm value
can wake up core power supply
registers RTT_MR,AR,VR,SR (mode alarm value status)
Prescalar used to "step down the timer"
Real-Time Clock: RTC
BCD counter (designed for gergorian calendar)
support years 1900 to 2099
Supports a 12 or 24 hr mode
One alawm can be programmed and trigger interrupt
Watchdog Timed: WDT
Timer Counter: TC
Contains TC0,TC1 and TC2
pulse width modulation
Five internal clock signals derived from MCK/SCK
three external (from pins)
Two user configurable input/output signals
Capture mode (for outside events)
waveform mode (to generate pulses or waveforms
In capture mode TIOA/TIOB are input
Floating/Fixed point Arithmetic
Main Idea: Extend the weighted number system with a binary point (radix point)
Standard; IEEE 754
NaN (not a number)
Denormalized: exponent is all 0s but the fraction is non-zero
PIOA/C enable: PMC_PCER0 bit 11/13