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Fetch-Decode-Execute Cycle - Coggle Diagram
Fetch-Decode-Execute Cycle
Fetch
PC stores the address
of the next instruction
Address is copied to MAR
Data
from memory
copied to MDR
Fetch instructions from
RAM to CPU
PC incremented
ready for next cycle
Decode
The
instruction in MDR
is
decoded by the CU
CU prepares for next step by loading values into MAR or MDR
Execute
CU sends signals to the registers to execute the instruction
load data from memory
do a calculation or logic operation using ALU
Change the address in the PC
or halt the program
CPU Components
The ALU
does all the calculations
Contains the accumulator
stores the intermediate results of calcualations in the ALU
performs logic operations and binary shifts
The cache
contains very fast memory
stored regularly used data so the CPU can access it quickly
Control Unit
controls the CPU
main job is to execute instructions in FED cycle
controls the fow of data to registers, ALU etc and outside
the CPU e.g main memory and input ouput.
contains the PC
holds the memory address of the instruction for each cycle.
Registers
MAR
Holds any memory ADDRESS about to be used by the CPU.
MDR
holds the actual DATA or INSTRUCTION.
PC
stores the address of the next instruction