Please enable JavaScript.

Coggle requires JavaScript to display documents.

CS chapter 1 - Coggle Diagram

- - - - 3.4 GHz is 3,400,000,000 cycles per second
        
        The higher the clock speed, the greater number of fde cyclels per second so higher performance
  - - - Much faster to access than RAM as it is much closer to registers that require the data.
        
        Also operates at a similar speed to the CPUP so little lag compared to retrieving data from ?RAM
        
        Contains levels of cache which differ in size and distance from the CPU
        
        Level 2 is in between 1 and 3 in terms of size and distance
        
        Level 3 Cache is furthest from the CPU and is the biggest
        
        Level 1 Cache is closest to the CPU, and is the smallest
        
        The reason all cache isn't level 1 is cost, as faster memory is more expensive
  - - - Each core can operate independantly, and each have their own low level cache as well has sharing high level cache
        
        different cores can run different applications at the same time, allowing more actions to occur each second
        
        However multiple cores does not always improve performance, as if a core is processing an instruction which is dependent on the processing of an instruction my another core, it will have to wait.
        
        This can cause hanging, where a core is wasted whilst it waits for the result of another instruction's execution
  - - - It operates in such a way that whilst the processer is decoding an instruction, the next instruction can be fetch from memoty
        
        works best in code where the next instruction is not dependent on the instruction before it
- - - - e.g. two numbers can be multiplied, but must each be in an individual register
  - - - contains the address of the next instruction to be executed
    - - Contains the address of the memory location currently in use
    - - Contains instructions/data to be executed
        
        There is a need for both of these as if there was no CIR, the MDR would hold the input instruction. However, when data is input, the inputted value would overwrite the input instruction in the MDR.
    - - Hold the instruction whilst it is decoded
    - - Stored the results of calculations processed my the CPU
- - - - The path along which data is transmitted, usually between the CPU and memory
        
        Half duplex pathway (data can travel in either direction but only one at a time
    - - When data is saved to / loaded from memory, the address of the memory location to be saved/loaded is also sent. This address is sent along the address bus.
        
        simplex pathway as CPU only ever sends the memory address, never receives it.
    - - The CU sends and recieves signals from all parts of the computer, ensuring all the processes occur at the correct time.
        
        These signals travel along the control bus which is made up of several control lines including a:
        
        interrupt-request line
        
        Memory read line
        
        Memory write line
        
        In addition to these lines, it also includes the clock for synchronizing operations
- - - - ALU deals with basic arithmetic such as binary addition or subtractions.
        
        capable of many complex mathematical functions e.g. sine, cosine, floating point division
- - - - decodes instructions during the FDE cycle
- - - - The address in the PC is copied to the MAR
      - The PC is incremented
      - A fetch signal is sent along the control bus by the CU to the memory, while the address held in the MAR is sent to the memory along the address bus and is held in the MDR
      - This value in the MDR is copied to the CIR
    - - The contents of the CIR are sent to the CU for decoding
        
        .
      - The type of addressing used by the instruction must be identified
        
        If the address is a direct address, load this address into the MAR and retrieve the contents of that address
        
        If the address is an indexed address, add the contents of the index register to the address, then copy this value to the
        MAR. Retrieve contents of this memory location
    - - If the instruction is a jump
        
        Load the address operand into the program counter and copy the address component in the CIR to the PC
        
        Finished
      - Otherwise, execute the instructions
        
        .