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1.1 CPU (Components (Cache (Fast SRAM, Most recently used data or…
1.1 CPU
Components
ALU
Arithmetic Logic Unti
Arithmetic - binary add or shift
Logic - boolean / bitwise NOT,AND,OR
Increments PC in the FETCH phase
Connected to the ACC register
CU
Control Unit
Controls the flow of data
within CPU between registers
between CPU and RAM
Controls the flow of instructions
Between RAM and CPU
Carries out the FDE Cycle
Registers
Specific Purpose
Instruction
PC- Program Counter
IR
MAR- Memory Address Register
MDR - Memory Data Register
Data
MDR
ACC - Accumulaote
MAR
See FDE Cycle Mindmap
A few bytes (32 bit / 64 bit) etc
very fast SRAM
Each CORE has its own registers
Cache
Fast SRAM
Most
recently used
data or instructions.
KB or MB in Size
L1 cache is fastest (and closest to its CPU core)
L1 cache is normally HARVARD in architecture
General CPU cache is von Neumann in Architecture
Buses
Data
2 way bus
MDR width affects size
Width affects instruction size
data/instruction Read: MDR <-- RAM
(Data) Write: MDR --> RAM
Address
CPU --> RAM
MAR width affects size
Width affects how much RAM can be addressed
Control
2-way bus
Controls READ/WRITE FROM/TO RAM
Accepts signals from other devices
wires connecting components (eg. CPU and RAM)
Von Neumann
One memory store
for both Data
and Instructions
Harvard
two memory stores
dedicated Data memory store
dedicated Instruction memory store
Micro level model (inside multi cored) CPUs
Each cores has a dedicated instruction cache and data cache
Macro level model of modern computer systems
Purpose
Carry Out FDE Cycle
Fetch (Binary) Instructions from RAM
Decode the (machine/binary) instruction
ALU performs arithmetic or logic
Data written back to RAM
Controls all other hardware components
FDE Cycle
seperate mind map