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1.2 Factors Affecting The Processor (2 types of processing (Pipelining,…
1.2
Factors Affecting The Processor
Dedicated Registers
Program counter (PC)
– holds the memory address of the next instruction to be executed
Current Instruction Register (CIR)
– holds the current instruction, which is split into opcode and operand
Memory Address Register (MAR)
- holds the address in memory where the processor is required to fetch or store data from or to
Memory Data Register (MDR)
– temporarily holds data moving between the processor and main memory
Accumulator
– to hold intermediate results of an instruction
Words
Memory is divided up in equal units called words
Word length is usually 8, 16, 32 or 64 bits
Each word has a separate memory address
What would be the memory capacity in bytes of a machine with an 8-line address bus and a word length of 8 bits?
Address Bus
The width of the address bus determines the maximum possible memory addresses of the system
With an 8-bit address bus, the maximum number of memory addresses is 28 = 256
An average PC has a memory capacity of
4 GiB (gibi bytes), which is 232 bytes
Therefore, it must have a 32-bit address bus
Data Bus
The data bus is bi-directional as data can be sent both ways along the bus
•The width of the data bus is defined by the number of wires
or lines it contains
If the data bus is the same width as a computer word, data can be transferred to and from memory in a single operation
Machine Code Instruction
The basic structure of a machine code instruction is shown, and given below in hexadecimal:
C50D ;load contents of accumulator into location 0B
The equivalent assembly code instruction could be:
LDA #13
The maximum size of the operand will depend on the width of the address bus
2 types of processing
•Parallel processing
•Pipelining
Parallel Processing
Using several processor cores working at the same time is known as parallel or concurrent processing
In systems designed for parallel processing, each core can work concurrently on different parts of the same task
Since instructions are processed sequentially, this is not always possible
Pipelining
This is a technique used to improve performance, for example by overlapping stages in the fetch-execute cycle,
or by breaking down the stages in an arithmetic instruction
An instruction enters the pipeline, and as soon as one stage has been completed, another instruction enters the pipeline
A third instruction then enters before either of the others is completed
There may be 10 or 12 stages in the pipeline, with some stages taking longer than others
