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Meinerzhagen, P., Teman, A., Giterman, R., & Burg, A. (2013).…
Meinerzhagen, P., Teman, A., Giterman, R., & Burg, A. (2013). Exploration of Sub- V T and Near- V T 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling, 54–72. https://doi.org/10.3390/jlpea3020054
NOTES
Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption.
Many systems, such as biomedical sensor nodes and implants, are expected to run on a single cubic-millimeter battery charge for days or even for years
Typical storage capacity requirements range from several kb for low-complexity systems [2] to several tens of kb for more sophisticated systems
All these state-of-the-art sub-VT memories are based on static bitcells, while the advantages and drawbacks of dynamic bitcells for operation in the sub-VT regime have not yet been studied.
Conventional 1-transistor-1-capacitor (1T-1C) embedded DRAM (eDRAM) is incompatible with standard digital CMOS technologies due to the need for high-density stacked or trench capacitors.
One of the main objections to sub-VT gain-cells is the degraded Ion=Ioff current ratio, leading to rather short data retentiontimes compared with the achievable data access times
while local parametric variations directly compromise the reliability of the SRAM bitcell (write contention, and data loss during read), such parametric variations only impact the access and retention times of gain-cells, which is not a severe issue when targeting the typically low speed requirements of ULP applications.
While the basic two-transistor (2T) bitcell has the smallest area cost, it limits the number of cells that can connect to the same read bitline (RBL) due to leakage currents from unselected cells masking the sense current.
METHOD
demonstrated on a 2 kb array, operated at 1 MHz
OBJECTIVES
presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain.
Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node.
propose full gain-cell arrays for each of the nodes, operated at a minimum VDD.
For the first time, we present a gain-cell array operated in the sub-VT domain.
CONCLUSIONS
We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV providing read/write availability over 99% of the time, despite refresh cycles.
RESULTS
As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97%read/write availability due to higher leakage currents that limit the bitcell’s retention time.
Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.
We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV providing read/write availability over 99% of the time, despite refresh cycles.