Giterman, R., Fish, A., Geuli, N., Mentovich, E., Burg, A., Teman, A., & Gan, R. (2017). An 800 Mhz Mixed- V T 4T Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications, 1, 308–311.
NOTES
sub-65 nm technologies suffer from much shorter DRTs due to the reduced parasitic storage capacitances and increased leakage currents.
CONCLUSIONS
The results indicate that the 4T GC-eDRAM array can be operated with a refresh rate of 5 μs with 99% of the bits providing reliable data retention (93% memory availability).
Approximate storage offers a compromise between improvedmemory density and power to decreased reliability, which can be tolerated by approximate computing applications.
METHOD
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the feedback and read transistors (NF and NR) are implemented using low-VT devices, to enable a faster evaluation of the RBL voltage during read, resulting in a much faster read access time.Moreover, the low-VT NF transistor strengthens the internal feedback of the cell, resulting in improved DRT characteristics.
RWL and VDD lines routed in M3, and a WWL routed in poly.
A redrawn 6T SRAM in the same technology node was measured at 0.26 μmx1.3 μm (0.338 μm2), 34% larger than the proposed 4T bitcell.
For comparison, a similar sized, singleport with “pushed-rule” bitcell layout, has a total silicon footprint of 42 μmx68 μm, which is over 40% larger than the proposed macro.
VBOOST and VREF were set to 1.2V and 0.8V, respectively. All measurements were performed under worst-case biasing conditions
OBJECTIVE
In this paper, we present the first fabricated and fully functional GC-eDRAM in a 28nm bulk CMOS technology.
The array, which is based on a novel mixed-VT 4T bitcell, can be used in both traditional and for approximate computing applications, featuring a small silicon footprint and supporting high-performance operation.
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RESULT & FINDING
Silicon measurements demonstrate successful operation at 800 Mhz under a 900mV supply, while retaining almost 30% lower area than a single-ported 6T SRAM in the same technology.
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4T bitcell, measured at 0.4 μmx0.63 μm (0.252 μm2), composed of two low-VT transistors (NF and NR) and two regular-VT transistors (NW and NB).
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At the nominal technology supply voltage of 0.9V the memory was successfully operated at the entire frequency range from 100 Mhz to 800 Mhz.
As expected, the DRT decreases with temperature due to the increase in leakage currents.
the average DRT of the array at 85C is 250 μs, the DRT distribution is spread across three orders of magnitude, resulting in a worst-case DRT of almost 1 μs.
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The DRT obtained for the implemented array may be small for memory applications for instruction or data caches.
demonstrating the errors in the picture stored in the array under different refresh rates, ranging from 1 μs to 50 μs, with corresponding refresh power components of 179 μW to 3 μW, respectively. The average PSNR was found at 66.1 dB, 59.2 dB, 52.3 dB, and 14.8 dB for refresh rates of 1 μs, 5 μs, 10 μs, and 50 μs, respectively.