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Structure and Function of the Processor (ALU, CU, Registers, Buses and…
Structure and Function of the Processor
Clock Speed, Number of Cores, Cache:
Cores: A core is an independent processor that is able to run its own fetch-execute cycle. A computer with multiple cores can complete more than one fetch-execute cycle at any given time.
A computer with dual cores can theoretically complete tasks twice as fast as a compute with a signal core. However not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this is not always possible.
Cache Memory: The CPU's onboard memory. Instructions fetched from main memory are copied to the cache, so if required again, they can be accessed quicker. As cache fills up, unused instructions are replaced.
Level 1 - Very fast memory cells with a small capacity (2 - 64KB)
Level 2 - Relatively fast memory cell, with a medium sized capacity (256KB - 2MB)
Level 3 - Much larger and slower memory cell
Clock Speed: The clock speed is determined by the system clock. This is an electronic device which generates signals, switching between 0 and 1. All processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1. The clock speed is the time taken form one clock cycle to complete.
The greater the clock speed, the faster instructions will be executed.
Von Neumann, Harvard and Contemporary Processor Architecture:
Von Neumann:
Cheaper to develop as the CU is easier to design.
Programs can be optimised in size.
One bus is used to transfer data and instructions.
Data and programs share the same memory.
Used in conventional processors in PCs, servers and embedded systems with only control functions.
Harvard:
Quicker execution as data and instructions can be fetched in parallel.
Memories can be different sizes, which can make more efficient use of space.
Programs tend to be large.
Parallel data and instruction buses may be used.
Instructions and data are held in separate memories.
Used in digital signal processing in embedded systems, mobile communication systems, audio, speech and image processing systems.
Contemporary: Contemporary processors use a combination of Harvard and Von Neumann architecture. Von Neumann is used when working with data and instructions in main memory, but uses Harvard architecture to divide the cache into instruction cache and data cache.
Pipelining:
Pipelining is a technique used by some processors to improve performance.
Pipelining is the process of completing the fetch, decode and execute cycles of three separate instructions simultaneously, close proximity to the CPU until it's required. While one instruction is being executed, another can be decoded and another fetched.
Pipelining is aimed to reduce the amount of the CPU which is kept idle. It is separated into instruction pipelining and arithmetic pipelining. Instruction pipelining is separating out the instruction into fetching, decoding and executing. Arithmetic pipelining is breaking down the arithmetic operations and overlapping them as they are performed.
Fetch-Decode-Execute Cycle:
Fetch:
Address from the PC is copied to the MAR.
Instruction held at that address is coped to the MDR by the data bus.
Simultaneously, the contents of the PC are increased by 1.
The value held in the MDR is copied to the CIR.
Decode:
The contents of CIR are split into operand and opcode.
Execute:
The decoded instruction is executed.
ALU, CU, Registers, Buses and Assembly Language:
Buses are set of parallel wires which connect two or more components inside the CPU. The three buses are called the system bus. The width of the bus is the number of parallel wires the bus has. The width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time.
Address Bus - This is the bus used to transmit the memory addresses specifying where data is to be sent to or retrieved from.
Control Bus - This is a bi-directional bus used to transmit control signals between internal and external components. The control bus coordinates the use of the address and data buses and provide status information between system components.
Bus Grant - shows that the CPU has granted access to the data bus.
Memory Write - data is written into the addresses location using this bus.
Bus Request - shows that a device is requesting the use of the data bus.
Memory Read - data is read from a specific location to be placed onto the data bus.
Clock - used to synchronise operations.
Interrupt Request - shows that a device is requesting access to the CPU.
Data Bus - This is a bi-directional bus. This is used for transporting data and instructions between components.
The Control Unit is the component of the processor which directs the operations of the CPU. It has the following jobs:
Controlling and coordinating the activities of the CPU.
Accepting the next instruction.
Managing the flow of data between the CPU and other devices.
Decoding instructions.
Storing the resulting data back in memory.
Registers are small memory cells that operate at a very high speed. They are used to temporarily store data and all arithmetic, logical and shift operations occur in these registers:
Accumulator - Stores the results from calculations.
Memory Data Register - Temporarily stores data that has been read or data that needs to be written.
Program Counter - Holds the address of the next instruction to be executed.
Current Instruction Register - Holds the current instruction being executed, divided up into operand and opcode.
Memory Address Register - Holds the address of a location that is to be read from or written to.
The ALU (Arithmetic and Logic Unit) completes all the arithmetical and logical operations. Arithmetical operations include all mathematical operations such as addition and subtraction on fixed or floating point numbers. Logical operations include Boolean logic operations such as AND, OR, NOT and XOR.
Assembly code uses mnemonics to represent instructions. This is a simplified way of representing machine code. The instruction is divided into operand and opcode in the Current Instruction Register. The operand contains the data or address of the data upon which the operation is to be performed. The opcode specifies the type of instruction to be executed.