Ganapathy, S., Teman, A., Giterman, R., Burg, A., & Karakonstantis, G. (2015). Approximate Computing with Unreliable Dynamic Memories, 1–4.
NOTES
The memory availability and standby power overhead are further worsened due to the insistence of traditional approaches on determining the frequency of the refresh cycles based on a worst-case assumption for the retention time of the most leaky cell, constantly biased at rare worst-case conditions.
approximate computing paradigm, in which the error resilient nature of many applications is exploited to relax the design constraints and save power.
includes the development of processors and software, may not always produce 100% precise results, but their output fidelity is acceptable for human consumption with significantly reduced power consumption.
For process technologies above approximately 100 nm DRT of the 2T GC-eDRAM bitcell was in the order of milliseconds, as the subthreshold leakage of MOS devices was relatively low and the parasitic capacitance could be significantly increased through metal stacking.
the effectiveness of metal stacking has been impeded by the introduction of low-k interconnect dielectrics, and the subthreshold leakage has significantly increased primarily due to short-channel effects (SCE) and drain-induced barrier lowering (DIBL).
the increasing process variations that characterize scaled technologies, as small deviations in the device threshold voltage have an exponential effect on the subthreshold leakage.
RESULTS & FINDING
Results indicate that by allowing as many as 177 errors in a 16 kB memory, the maximum loss in output quality is 11%.
For memories with a cell-failure rate as high as 10−3, the observed loss in output quality is below 10%.
the inherent error resilience of KNN is much better than that of EN, as evinced by the fact that for a failure probability as high as 10−3, the quality is almost 97% of the quality obtained when executed on a fault-free memory.
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For the 65 nm process, the reduction of retention power approaches 5× by allowing an error probability of Perr < 10−3, and all processes benefit by at least 2×.
OBJECTIVE
In this paper, we consider extending the refresh period of gain-cell based dynamic memories beyond the worst-case point of failure, assuming that the resulting errors can be tolerated when the use-cases are in the domain of inherently error-resilient applications.
We evaluate the benefits of lowering refresh frequency in the context of enhancing memory availability and also study the impact on output quality for two data-miningapplications executed on such an error-prone memory.
CONCLUSION
during low activity (standby) periods, the refresh operations are the primary source of power consumption in GC-eDRAM memories.
Our analysis, reveals that while the increase in availability for mature technologies is negligible, a large benefit can be achieved through the proposed refresh rate relaxation be achieved through the proposed refresh rate relaxation
METHOD
For example, we observe that for various data mining applications, a large number of memory failures can be accepted with tolerable imprecision in output quality, we use such failure limits to study the impact of relaxing reliability constraints on memory availability and retention power for different technologies.
Analysis of a 2T gain-cell array in the context of technology scaling, revealing diminishing retention times with technology advancement.
Evaluation of the error tolerance limits for two popula
data-mining applications. K-nearest neighbors (KNN) and elastic net (EN). KNN and EN are used extensively in the machine learning domain for building classification and regression models, respectively. The benchmarks were developed using the popular open-source machine learning framework, Scikit-Learn.
used real world datasets for the training and testing phases of the benchmark execution [9], partitioned into training and testing inputs (0.8:0.2), and executed themon a 16 kB simulated memory.