Meinerzhagen, P., Teman, A., Fish, A., Burg, A., & Tcl, S. T. I. I. E. L. (2013). Impact of body biasing on the retention time of gain-cell memories, 1–4. https://doi.org/10.1049/joe.2013.0057
NOTES
OBJECTIVE
CONCLUSION
RESULT & FINDING
METHOD
This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block.
examines the distribution of the retention time across the entire gain-cell array.
The concept is demonstrated through silicon measurements of a test chip manufactured in a logic-compatible 0.18 μm CMOS process.
the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.
GC-eDRAM has decoupled read and write ports
The application field of gain-cell-based eDRAM is broad, ranging from high-speed caches in microprocessors to ultra-low power systems
Simple measures to extend DRT
increasing CSN through layout techniques
minimising the subthreshold conduction through the write access transistor (MW) by using low-leakage MOS transistors
employing write bitline (WBL) control schemes to minimise charge loss through MW
An additional technique that has not yet been applied to gain-cells is threshold voltage (VT) adjustment through body biasing (BB).
the application of a reverse BB (RBB) raises VT and therefore reduces the charge loss through subthreshold conduction, this means of control can also improve the array availability by applying a forward BB (FBB) during refresh cycles to reduce access time
proposes reverse BB as a technique to improve the retention time of gain-cell memories and demonstrates its high effectiveness by means of silicon measurements.
Moreover, the retention time penalty of forward BB, used for fast memory access and short refresh times, is evaluated.
The dominant leakage mechanism that causes the deterioration of the stored data levels is clearly the subthreshold conduction of MW.
This is especially true for mature CMOS nodes, such as the 0.18 μm process used in this study, but also holds for a deeply scaled 40 nm CMOS node.
In order to achieve the longest possible retention time, an I/O PMOS transistor is used to implement MW, as this device features the lowest subthreshold conduction among all devices offered in the chosen 0.18 μm CMOS technology
fig1b. The core bitcell array consists of 64 × 32 gain-cells, all sharing the same n-well and VB. n-Well contacts are provided every 16 rows, as well as at the top and the bottom of the array..
fig1b. In addition to the bitcell array, the macrocell comprises the following peripheral circuits: (1) a write address preand post-decoder that drives VDD or –VNWL onto WWL; a read address pre- and post-decoder that drives VDD or VSS onto RWL, level-shifters, WBL drivers, readout sense buffers and timing control units.
In addition to the 2 kb gain-cell macrocell in the lower left corner, the chip contains a built-in self test (BIST) unit. The main features of the BIST can be summarised as follows:Finally, the test chip also contains scan chains for full access to
(1) address sequence generation (increasing, decreasing and pseudo-random);
(2) data pattern generation (checkerboard, pseudo-random and all-‘1’, all-‘0’);
(3) programmable refresh period of the memory under test (MUT);
(4) pass/fail decision during readout of the MUT;
(5) SRAM for storing maps of MUT retention time, read failures, or write failures;
(6) support for two-port operation of the MUT.
Finally, the test chip also contains scan chains for full access to the MUT with any data or address sequence pattern independent of the BIST.
The packaged test chips were mounted on a test board by means of a burn-in socket and connected to a TMPC PG3A pattern generator and a Tektronix TLA6403 logic analyser. The main supply of the memory macrocell was set to 750 mV,and the body voltage VB was swept from 500 to 875 mV to analyse the impact of BB. At room temperature (temperature
was not controlled).
A separate negative voltage of –1.5 V was supplied to the macrocell for the WWL underdrive.
The BIST and other digital control units were supplied with the technology’s nominal voltage of 1.8 V.
Both the write and read access times were set to 1 μs for robust write and read operations, even at the low VDD of 750 mV, to ensure that the measured failures relate to retention time, and were not caused by incomplete writes or erroneous reads because of insufficient access time.of insufficient access time.
The cell-to-cell retention time variability is high, ranging from 23 to 569 ms under standard body biasing (SBB). corresponding to a ratio of 25 between the maximum and minimum values, A recent study [8] reports an even higher ratioof over 50 between the maximum and minimum measured retention times in an 1 kb array implemented in 65 nm CMOS.
the absence of a systematic pattern in the measured retention time maps suggests that the high variability is caused by local parametric variations, which are particularly high in memory arrays because of the use of minimum-size devices.
the process parameters of I/O devices, used to achieve high retention times, may be less carefully controlled than those of core transistors.
RBB is an attractive technique to improve the minimum (as well as the average) retention time.
the retention time penalty for FBB (used for fast memory access) is high, exhibiting a 2.9 × reduction for 100 mV FBB.
a possible control scheme could dynamically apply an RBB during retention periods and an FBB during refresh cycles to maximise array availability.
The measured retention time of a 2 kb memory macrocell is improved by 2.3 × (from 23 to 53 ms) with a RBB of only 100 mV.
Measurements indicate that the two-PMOS gain-cell retains logic‘1’ levels for extensive periods ( > 1 s), even when the WBL is held at 0 V (which maximises the subthreshold conduction of MW).
the gaincell’s retention time is almost exclusively limited by its ability to hold a logic ‘0’ level. The decay of a cell’s logic ‘0’ level is heavily dependent on the state of the WBL.
Our measurement setup assumes a 50% write duty cycle (i.e. there is a write access during 50% of the time) and that the probability of writing a ‘1’ (which requires pulling WBL up to VDD) is 50% as well. Overall, this leads to a write-‘1’ disturb activity factor (αdisturb) of 25%.
in the present study, the majority of the cells exhibited retention times in the range of 20–200 ms whereas a small number of cells exhibited considerably higher retention times.
There is no systematic pattern, indicating that the retention time variability arises from local (within die), random process parameter variations.
The impact of BB on the measured retention times was evaluated by sweeping VB from 500 to 875 mV (−250 mV < ΔVB < 125 mV).
As expected, the best cells with the highest retention time remain at the same location under varying VB.