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Teman, A. et al. (2014) ‘Replica Technique for Adaptive Refresh Timing of…
Teman, A. et al. (2014) ‘Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM’, 61(4), pp. 259–263
NOTES
The majority of the target applications for such memory deviceshave been large caches that benefit from the reduced transistorcount of GCs.
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the use of a high-voltage-threshold transistor or an input/output (I/O) transistor is the best choice for the implementation of a GC’s WRITE transistor.
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DRTs are generally measured for extreme worst-case conditions in terms of Process–Voltage–Temperature (PVT) and operational behavior.
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CONCLUSION
Previously, not taking into account the actual levels of WBL during operation. As a result, when operating on real data, refresh cycles will be initiated well before the actual stored data approaches hazardous levels.
Four primary factors affecting DRT, all these factors are affected by environmental and manufacturing variations
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Traditional, worst-case design assumes 100% WRITE activity, resulting in a retention period of well below 10 ms
OBJECTIVE
present a replica technique for automatically tracking the retention time of a gain-cell-embedded dynamic-random-access-memory macrocell according to process variations and operating statistics,thereby reducing the data retention power of the array.
propose a replica technique for tracking both the PVT variations of a GC-eDRAM macrocell, as well as the acute characteristics of the data access to adaptively time refresh operations.
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METHOD
A 2-kb array was designed and fabricated in a mature 0.18-μm CMOS process,
An additional post-silicon calibration step is added to the refresh controller to skew the DRT below the measured worst-case DRT of the array. This is done by employing periodic pseudo-WRITE cycles to the replica column. This is to adjust the tracking mechanism for each die to handle local variations.
a column of replica cells is integrated with the GC-eDRAM array and is periodically read out to analyze the state of the array’s data retention, designed with slightly reduced CSN (less metal stacking
above the bit cells).
With proper post-silicon calibration of the WRITE frequency to these replica cells, they can be adjusted to fail before the worst data cell in the array, while tracking the PVT variations of the fabricated array.
the replica column is designed to track the access statistics of the array, rather than assuming unlikely worst-case conditions
Testing and characterization of the replica technique was implemented with an on-chip controller, incorporating the finite state machine (FSM)
**RESULT & FINDING
Measurements show efficient retention time tracking across arange of supply voltages and access statistics, lowering the refresh frequency by more than 5× with 10% WRITE activity, as compared with traditional worstcase design.
the replica columns led to an overall area overhead of only 6.25%, without significantly affecting the READ and WRITE access times.
The GC-eDRAM bit cell was laid out in a compact array with
mirrored rows and columns with a unit cell size of 3.024-μm2 (1.8 μm × 1.68 μm).
The array, including peripheral circuits, occupies 0.013 mm2 (106 μm × 129 μm) and is biased by a separate low-voltage supply (MVDD) different than the supply (VDD) of the BIST and the other digital peripheral circuits of the test chip.
In addition, an external negative voltage (VNWL) is supplied for the WRITE underdrive.
the active refresh power of the array
is 635 fW/bit, which is comparable with similar low-powerGC-eDRAM publications