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Giterman, R. et al. (2016) ‘A Process Compensated Gain Cell Embedded-DRAM…
Giterman, R. et al. (2016) ‘A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design’, pp. 1006–1009
NOTES
The worst-case biasing conditions assume continuous write operations to the array, while the actual DRT is significantly affected by the access statistics of the array
Several previous works
Reverse body biasing (RBB) is applied to GC-eDRAm array to limit the subthreshold leakage through the write transistor
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Tracking both the process-voltage-temperature (PVT) variations of the chips and the access statistics of the array to develop an adaptive refresh timing
Suggested the use of high VT I/O write transistor to reduce the sub-VT leakage for energy efficient array implementation
RESULT & FINDING
Providing as much as 7x reduction in retention power over worst-case refresh-rate design for 20% write activity.
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2x faster write access time, compared to using an I/O MW.
CONCLUSION
The refresh rate, which is set according to the extracted DRT, is much higher than the actual data retention of the array under given operating conditions and access characteristics.
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The DRT is highly dependent on device threshold voltage (VT), therefore when taking all variations into account in across thousands of arrays/bitcells, the worst-case DRT becomes too low, might even cause loss of array availability beyond acceptable rates.
Measurements of previous 2kb GC-eDRAM arrays shows that array mismatch causes DRT variation over two orders of magnitude
METHOD
A 1KB (128x64) GC-eDRAM macrocell was implemented in a mature 0.18um CMOS process using only sandard-VT devices.
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OBJECTIVE
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Present a novel GC-eDRAM architecture, incorporating several techniques for variation-aware operation (body-biasing, dual-readout functionality), with addition of improved immunity to variations through process compensation
replica scheme for process compensated access tracking that enables calibration for process variations and adaptive refresh according to the array access statistics