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Maltabashi, O. et al. (2018) ‘A 5-Transistor Ternary Gain-Cell eDRAM with…
Maltabashi, O. et al. (2018) ‘A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing’ IEEE International Symposium on Circuits and Systems (ISCAS)
NOTES
GC-eDRAM
Advantages
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the lack of internal feedback potentially provides the opportunity to store multiple voltage levels and thereby increase the perbit area and energy-efficiency of the memory.
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6T SRAM
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Disadvantages
the bi-stable nature of SRAM while providing robustness, limit this technology to the storage of a single bit of data, as opposed to other technologies.
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In order to support low-voltage operation, higher area and leakage power overheads
mutlilevel storage is a popular approach for nonvolatile memories and has been proposed for off-chip DRAM it is seldom discussed in terms of on-chip embedded memory
CONCLUSION
The storage of multiple voltage levels in the memory cell significantly reduces the voltage difference between every two levels, ultimately reducing the DRT of the memory cell..
The proposed memory utilizes low overhead write and read peripherals to store and readout three distinct logic values in an area and energy-efficient fashion.
RESULTS AND FINDING
provides over 3x reduction in static power, as compared to the static power of a 6T
SRAM
area of 0.938um2 (0.92umx1.02um), 48% reduction of area-per-bit in comparison with a conventional SRAM cell in the same technology.
The estimated DRT of the TGC is 0.354 ms and 0.5 ms for 27C and 85C, respectively, under worst-case biasing conditions.
The total retention power per bit (leakage plus refresh power) of a 16 kb (128x128) memory macro, is 227.9pW at 85C.
These values are calculated as the first time that two curves which stores different voltage value have a 350mV difference.
OBJECTIVE
suggest a novel GC-eDRAM topology that is capable of storing three voltage levels within a single cell
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Previously, it involves a very complex sensing scheme, requiring the generation of reference voltages using charge sharing
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two special peripheral circuits – a WBL driver and a half VDD generator – to accommodate the ternary write requirement were proposed.
METHOD
proposed ternary based on a 5-transistor (5T) GC-eDRAM bit-cell, is designed in a standard CMOS 65nm technology node.
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using a parallel sensing scheme composed of skewed sense inverters for ternary readout, using a pair of sense inverters with different switching thresholds in order to differentiate between the three possible memory states.
The write voltage generation and drivers are based on low-overhead, per-row write peripherals, avoiding the usage of complex and time-consuming charge sharing techniques.
post-layout simulations are used to demonstrate the successful operation of the proposed array under mismatches.