Giterman, R., Teman, A. and Fish, A. (2018) ‘Ultra-Low Power IoT Applications in 28nm FD-SOI’, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 3, pp. 1–2
NOTES
CONCLUSION
OBJECTIVE
METHOD
RESULT & FINDING
Internet of Things (IoT) applications, such as biomedical sensing, often require on-chip embedded memories, which dominate both,
silicon area
power of these applications
supply voltage (VDD) scaling down to the sub-threshold voltage (VT) region can be used to significantly reduce both,
Static power consumption
Dynamic power consumption
6T SRAM embedded memories
suffer from decreased noise margins
become unreliable at near-VT supply voltages
GC-eDRAM
Advantages
Disadvantages
fully logic-compatible
can consume lower retention power than SRAM
offers smaller area
requires periodic refresh cycles to maintain its data
technology scaling has led to increased leakage currents and decreased capacitances
lower data retention times
limiting the VDD of these memories to the near-VT domain
propose exploiting the efficient bodybias capabilities of 28 nm FD-SOI technology, often targeted at energy-efficient IoT applications.
low leakage characteristics
opposite polarity (negative) of the main sub-VT supply.
strongly suppressing the leakage currents of the bitcell
Increasing its DRT.
This paper presents the first sub-VT GC GCeDRAM implementation in a 28 nm node.
The implemented memory demonstrates successful operation at a 400mV supply, which is the lowest among conventional sub-VT memory implementations
in the considered technology.
read and write devices can be implemented with any type of transistor
Regular-VT and minimal sized NMOS and PMOS transistors were selected for the implementation of the write and read devices, respectively
RBL has a limited swing when reading a ‘0’, as it saturates at a voltage lower than VDD due to leakage from unselected cells in the column.
To strongly suppress the sub-VT leakage from the SN, reversed body-bias is applied to MW, with its bulk voltage (VBB) connected to –VDD (–400 mV).
during standby and read cycles, the WWL is discharged to –VDD to further decrease the overdrive of MW (VGS − |VTn|).
NMOS write transistor enables the usage of a single power supply and its negation for enhanced retention time characteristics.
PMOS read transistor results in a better read access time than with an NMOS since the ‘0’ voltage level has a slower data degradation due to leakage and its initial value after write is GND
WWL routed in Poly for decreased capacitance
RWL routed in M2, and RBL and WBL routed in M3.
The cell was measured at 0.51 μm×0.27 μm (0.138 μm2), which is almost 50% smaller than a redrawn 6T SRAM in the same technology.
A 128×64 bit (4 kb) memory macro based on the 2T GC-eDRAM cell was designed in a 28 nm FD-SOI process.
The level degradation with the negative biasing is more than two orders of magnitude higher, estimated at 0.9 ms, due to the strongly suppressed sub-VT leakage as a result of the negative MW overdrive.
Refresh power of the cell,under worst-case leakage biasing conditions with the negative voltage applied to the gate and body of MW during hold is as low as 14.3 pW/bit at 25◦C, assuming a retention
time of 0.9 ms.
lower than than leakage power of the other cells, ranging from 17.6 pW/bit – 19.1 pW/bit, due to their higher transistor count.
the proposed 2T cell is much smaller than the other ULP memory options, ranging from 2.5× – 3.8× lower bitcell area.