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Giterman, R. et al. (2015) ‘A Soft Error Tolerant 4T Gain-Cell Featuring a…
Giterman, R. et al. (2015) ‘A Soft Error Tolerant 4T Gain-Cell Featuring a Parity Column for Ultra-Low Power Applications’, pp. 0–1
NOTES
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SEUs occur when an energetic particle passes through a silicon substrate and its energy is transferred into the creation of electron-hole pairs along its path, It might cause data flip of a memory cell.
SRAM based solutions, SEUs are typically handled at an architectural level using redundancy schemes, such as error correcting codes (ECCs) and triple modular redundancy (TMR)
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CONCLUSION
The primary risk of an SEU triggered data flip in a conventional SRAM cell is due to the positive feedback between the two internal storage nodes that are susceptible to particle strikes.
the GC-eDRAM bitcell lacks this internal feedback, and for the all-PMOS cell of the only node susceptible to a strike is the reverse biased p+n junction at SN. For such a junction, only a positive voltage shift can occur due to a particle strike.
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RESULT AND FINDING
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Much smaller than alternative rad-hard bitcells, such as DICE or Quatro 10T.
The area of one bitcell is 5.264 μm2, which is only 52% of a redrawn 6T SRAM in the same technology node.
showed full functionality at a wide range of voltage supplies, including 400 mV sub-threshold voltage
For correct power analysis, the refresh period was chosen to be 500μs, which ensures cell functionality under all simulated cases.
The refresh power constituted 40% to 60% of the total power consumption of the 4T cell, depending on the supply voltage.
OBJECTIVE
Present a novel solution to embedded memories used in high radiation environments based on a GC-eDRAM, combining both circuit and architectural techniques to provide a soft error tolerant memory, designed for ULP applications.
METHOD
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In order to exploit this behavior to provide robustness to SEUs, duplication of the standard 2T cell into the four transistor (4T) structure was proposed.
if both storage nodes provide the same read out level (presumably a data ‘1’), it can be concluded that a disruptive SEU occured.
a parity column is integrated to the memory array. These cells are identical to the 4T bitcells and hold the parity bit of the corresponding row. Using simple comparison logic, the correct data can be easily recovered from an error detected cell.