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Chapter 4 The IA-32 Architecture Guide to Assembly Language Programming…
Chapter 4
The IA-32 Architecture
Guide to Assembly Language Programming in Linux
Processor Execution Cycle
FETCH an instruction from the memory
DECODE the instruction
EXCECUTE the instruction
Processor Registers
Data Registers
AX
BX
CX
DX
Pointer and Index Registers
Control Registers
Segment Registers
3.Protected Mode Memory Architecture
Uses 32-Bit addresses and is the native mode of the IA-32 architecture
Segment Registers
Index
Table indicator
Request privilege level
Segment Descriptors
Base address
Granularity
Segment limit
D/B bit
Description privilege level
Type
P Bit
Segment Descriptor Tables
The global descriptor table
Local descriptor tables
The interrupt descriptor table
Real Mode Memory Architecture
The memory address space is 1 MB. To address a memory location, we have to use a 20-bit address.
Mixed-Mode Operation
The D/B indicates the default size,32-bit registers can be used in the 16-bit mode of operation The instruction set provides two size override prefixes; one for the operands and other for the addresses
Which Segment Register to Use
Instruction fetch
CS,IP or EIP
Stack operations
SS,SP,BP
Accessing data
DS
7.Input/Output
Used to communicate with the outside world and to store data
I/O Controller
If we use an I/O controller could provide the necessary low-level commands and data for the proper operation of the associated I/O device.
Using an I/O controller causes that the amount of electrical power used to send signals on the system bus is very low
Daniela Porras Quirós
2015071255