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CPU (Instruction Cycle (Indirect Cycle
May require memory access to…
CPU
Instruction Cycle
Indirect Cycle
- May require memory access to fetch operands
- Indirect addressing requires more memory access
- Additional instruction subcycle
Data Flow (Instruction Fetch)
- Fetch
- PC contains address of next instruction
- Address moves to MAR
- Address placed on address bus
- Control unit requests memory read
- Result placed on data bus, copied to MBR, then to IR
- Meanwhile PC incremented by 1
Data Flow (Execute)
- May take many forms
- Depends on instruction being executed
- May include:
- Memory read/write
- Input/Output
- Register transfers
- ALU operations
Data Flow (Interrupt)
- Simple, predictable
- Current PC saved to allow resumption after interrupt
- Contents copied to MBR
- Special memory location loaded to MAR, MBR written to memory
- PC loaded address
- Fetch next instruction
ARM
Attributes
- require fewer transistors than CISC
- reduces costs, heat and power use
- moderate array of uniform registers
- Load/store model
- Uniform fixed-length instruction
- Shift or rotation can pre-process source registers
- Small number of addressing modes
- Auto-increment and auto-decrement addressing
- Conditional execution minimizes conditional branches
Processor Organization
- Data exchanged between processor and memory through data bus
- Instructions go through decoder before execution
- Pipeline and control signal generation in control unit
- Data goes to register file
- Rotation or shift before ALU
Register Organization
- 37 x 32-bit registers
- 31 general-purpose registers
- 6 program status registers
- Registers in partially overlapping banks
- 16 numbered registers and one or two program status registers visible
General Register Usage
- R13 normally stack pointer (SP)
- R14 link register (LR)
- R15 program counter
Cycles
Fetch Cycle
- Address of next instruction is in PC
- Copy address in PC to MAR, then to address bus
- Control unit issues READ command
- Result appears on data bus
- Data copied to MBR
- PC incremented by 1
- Data moved to IR
- MBR is now free for further data fetches
Interrupt Cycle
- At the completion of the execute cycle, test is made to determine the occurence of interrupts
- If so, interrupt cycle occurs
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Registers Organization
Registers
- Working space for CPU (temporary storage)
- Number and function vary between processor designs
- Top level of hierarchy
Control & Status Registers
- PC (Program Counter)
- Instruction Decoding Register
- MAR (Memory Address Register)
- MBR (Memory Buffer Register)
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CPU Structure
- Fetch instructions
- Interpret instructions
- Fetch data
- Process data
- Write data
Loop Buffer
- Very fast memory
- Maintained by fetch stage of pipeline
- Check buffer before fetching from memory
- Very good for small loops or jumps
Branch Prediction
- Predict never taken
- Predict always taken
- Predict by Opcode
- Taken/Not taken switch
- Correlation-based