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Chapter 7: Processor Structure and Function (Pipelining (Fetch, Decode,…
Chapter 7: Processor Structure and Function
Processor
Organization
Interpret
Instruction
Fetch
Instruction
Fetch
Data
Process
Data
Write
Data
Register
Organization
Control & Status
Registers
Program counter
Decoding
Address
Buffer
Program Status
Word
Set of bits
Condition codes
Interrupt enable/ disable
Instruction Cycle
Fetch
Indirect
Execute
Interrupt
Pipelining
Fetch
Decode
Calculate
Fetch operand
Execute
Write result
The x86 Processor Family
Intel 80486
Fetch:
From cache
Decode 1:
Opcode
Decode 2: Expand opcode
Execute:
ALU operate
Writeback:
Result
Advanced
RISC
Machine
Attributes
Moderate
array
Load/store
Uniform Fixed length Instruction
Can preprocess
Source register
Small, auto increment & decrement addressing
Conditional Execution instruction
Processor Organization
Data (CPU-memory)
Data load/fetch @ store
Data decoded
Pipeline&control signal
In CU
Data goes to register
file
END
ARM register organization
37x32 bit
Six program status registers
31 general
Purpose register
Register in Partially over-lapping banks
16 number register & one or two program status registers visible