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Memory System (Cache Memories (Cache Inconsistency (Dirty data (Data in…

- - - - Data in the cache is modified but not in the main memory
    - - Data in the main memory is modified but not in the cache
- - - - Memories that can retain their states as long as power is supplied
      - 6 transistors per memory cell
    - - Very low power consumption
      - Fast access time
    - - Expensive
  - - - Do not retain their state for a long period, unless they are accessed frequently
      - Charge in a capacitor
    - - Simple/less complex memory cells (cheaper)
      - Higher density memory (small form factor)
    - - Periodic refreshment of its contents (require extra circuitry)
      - Slow access time
    - - Synchronous double data rate (DDR)
        
        Double data rate
        
        Memory operation with reference to the both clock edges
        
        Double the data transfer rate
      - Asynchronous DRAM
        
        similar with the synchronous DRAM
        
        Suitable for low speed memory bus systems
        
        No common clock for guiding data transfer operation
        
        Support several modes:
        
        Page mode
        
        Fast page mode
        
        EDO (extended data out)
      - Synchronous DRAM (single data rate, SDR)
        
        synchronized to a common clock signal
        
        Single data rate
        
        Operation on a single clock edge
- - - - written only once
      - Logic 0 when connected to ground, otherwise logic 1
    - - allows user to load some data
      - Programmability was using fuse, blowing it creates logic 0, keeping it creates logic 1
    - - allows the stored data to be erased and new data to be written into it
      - Erase method: using exposing to UV light
    - - Can be programmed, erased and reprogrammed electrically
      - Possible to erase the cell contents selectively
      - Does not have to be removed physically for erasure
- - - - For primary storage: access time to any location is the same, independent of location’s address
      - For secondary storage: access time depends on the address/position of data in the storage
    - - Minimum time delay required between the initiation of two successive memory operations
    - - Amount of time the memory takes to transfer a block of data
      - Depends on the transfer rate and the data block size