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Quartus (Timing (Cross-clock Timing Limitation, Routing Congestion ->…

- - - - P2: set_max_skew
        
        set_max_skew -from_clock { clock } -to_clock { * } -from foo -to blat 2
        
        Only set_false_path will overrides set_max_skew
      - P1: set_net_delay
        
        set_net_delay -max 0.500 -from inst8|combout -to *
        
        set_net_delay -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.9 -from inst8|* -to [get_keepers inst9]
        
        Applies Independently other settings, even set_false_path
    - - P0: set_false_path
      - P3: set_clock_groups
      - Highest precedence
      - P1: set_min_delay & set_max_delay
      - P2: set_multicycle_path
    - - clock related
      - set_input_delay
      - set_max_delay
      - set_output_delay
    - - Synchronizer chiains: ??
      - I/O boundaries: add wrapper
      - "preserve" synthesis attribute
      - Clock crossings(Multi-Clock Requirements)
      - RAMs & DSPs
      - Reg ctrl signals: Asynchronous clears/Synchronous Clears/Clock Enable
      - Latches
      - SDC exceptions: set_false/multicycle_path/max/min_delay
      - Power-up initial
      - HP chapter5