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Chapter 3: Input / Output ((4) Interrupts (Interrupt Process (Processor is…
Chapter 3: Input / Output
(1) Bus structure and operation
Disadvantage of bus system
Communication bottleneck
Maximum bus speed
Advantage of bus system
Versatility
Low cost
Define Bus
Processor, main memory, and I/O devices are interconnected
provides a communication path for the transfer of data.
General bus organization
3 functional group
Control lines
Use to control the access to and the use of the data and address lines
Address lines
To designate the source of destination of the data on the data bus
Data lines
Provide a path for moving data among system modules
(2) Arbitration
Why do we need arbitration
Relate to the bus structure
Who grants requests
Assign an arbitrator
Arbitration goals
Prevent more than one bus user at a time
Give all devices a fair chance to access the bus
Arbitration Methods
Centralized
Bus arbitration requires hardware (arbiter) that will grant the bus to one of the requesting devices
Decentralized
Decentralized arbitration there isn't an arbiter, so the IO devices have to decide who goes next.
Synchronous Bus
The master places the data on the bus along with the address and commands at time t0
The slave strobes the data into its input buffer at time t2
Bus Propagation Delay
Command on the bus, it takes time
For this information to propagate to the devices
Asynchronous Bus
Advantage
Eliminates the need for synchronization between the sender and the receiver
Can accommodate varying delays automatically, using the Slave-ready signal
Disadvantage
Data transfer rate with full handshake is limited by two-round trip delays.
Data transfers using a synchronous bus involves only one round trip delay, and hence a synchronous bus can achieve faster rates.
(3) Accessing IO devices
Explanation
Multiple I/O devices may be connected to the processor and the memory via a bus.
Each I/O device is assigned a unique address.
To access an I/O device, the processor places the address on the address lines.
The device recognizes the address, and responds to the control signals.
I/O Devices Synchronization
The rate of transfer to/from I/O devices is slower than the speed of the processor. This creates the need for mechanisms to
Synchronize data transfers
Program-controlled I/O
Processor repeatedly monitors a status flag to achieve the necessary synchronization
Processor executes a program that gives it direct control of the I/O operation
Processor issues a command it must wait until the I/O operation is complete
Interrupts-driven I/O
The problem with program-controlled I/O is that the processor has to wait a long time
The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor
Direct Memory Access (DMA)
Transfer a block of data directly between an I/O device and the main memory, without continuous intervention by the processor.
(4) Interrupts
In program-controlled I/O, when the processor continuously monitors the status of the device, it does not perform any useful tasks
Interrupt Process
Processor is executing the instruction located at address i when an interrupt occurs
Routine executed in response to an interrupt request is called the interrupt-service routine
When an interrupt occurs, control must be transferred to the interrupt service routine
But before transferring control, the current contents of the PC (i+1), must be saved in a known location
This will enable the return-from-interrupt instruction to resume execution at i+1
Return address, or the contents of the PC are usually stored on the processor stack
Interrupt Service Routine
Treatment of an interrupt-service routine is very similar to that of a subroutine process
Significant differences
A subroutine performs a task that is required by the calling program
Interrupt-service routine may not have anything in common with the program it interrupts
Interrupt Latency
Saving and restoring information can be done automatically by the processor or explicitly by program instructions
Saving and restoring registers involves memory transfers
Increases the total execution time
Increases the delay between the time an interrupt request is received, and the start of execution of the interrupt-service routine
Interrupt Acknowledge
When a processor receives an interrupt-request, it must branch to the interrupt service routine
It must also inform the device that it has recognized the interrupt request
Interrupt Polling
When a processor receives an interrupt request over this control line, the status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt
Priority
Interrupt Priority
Which interrupt request does the processor accept if it receives interrupt requests from two or more devices simultaneously
IO Device Priority
An interrupt request from a high-priority device is accepted while the processor is executing the interrupt service routine of a low priority device
Exceptions
Interrupts caused by interrupt-requests sent by I/O devices.
Interrupts could be used in many other situations where the execution of one program needs to be suspended and execution of another program needs to be started
(5) Interface circuits
Function
temporary storage of data
Performs format conversion (communication protocol)
information governing the behavior of the interface
address-decoding circuitry
timing signals
Parallel/Serial Ports
Parallel port
Transfers data in the form of a number of bits at a time, normally 8 or 16 to or from the device
Serial port
Transfers and receives data one bit at a time
(6) Interconnection standards
I/O device is connected to a computer using an interface circuit
Two widely used bus standards
Peripheral Component Interconnect (PCI)
The bus supports three independent address spaces: memory, I/O, and configuration
The master maintains the address information on the bus until data transfer is completed
A master is called an initiator, the slave is called a target
Universal serial bus (USB)
An industry standard developed by Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, Nortel Networks, and Philips
Evolution
USB 1.0: 1996, 1.5 Mbit/s (keyboard, etc), 12 Mbit/s (disk)
USB 2.0: 2000, 470 Mbit/s
USB 3.0: 2008, 5 Gbit/s
USB 3.1: 2014, 156 Gbit/s
PCI USB
Advantage
Low cost bus
Processor independent
Plug and play capability
DANIEL TAN BOON KAI
CE170189