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Chapter 3 : Input/Output (Accessing I/O Devies (I/O Commands (Control,…

- - - - main memory
      - I/O devies
      - Processor
    - - Versatility
      - Low Cost
    - - Communcation bottleneck
      - maximum bus speed
    - - Master: Starts the transaction
      - Slave : respond to the address
    - - Control lines
      - Address lines
      - Data lines
  - - - Bus types: dedicated, shared
        
        Dedicated : bus line is permanently assigned either to one function or to a physical subset of computer component
      - Arbitration methods : Centralize, decentralized
      - Timing : Synchronous, asynchronous
    - - Transfer the information on the bus once access is granted
      - Obtain the bus i.e. request to use the bus
      - If one component wants to send/receive data to/from another component, it must:
- - - - monitors a status flag
      - polls the I/O devices.
      - direct control of the I/O operation
      - issues a command it must wait until the I/O operation is complete
  - - - Memory-mapped I/O
      - Simpler software.
    - - Special instructions to transfer data to/from I/O devices.
      - I/O devices may have to deal with fewer address lines.
  - - - transfer a block of data directly between an I/O device and the main memory, without continuous intervention by the processor.
    - - To transfer a block of data
      - it provides the starting memory address and all the control signals.
- - - - similar to that of a subroutine process.
    - - time an interrupt request is received, and the start of execution of the interrupt-service routine.
      - save only the minimal amount of information
    - - inform the device that it has recognized the interrupt request
    - - may alter the intended sequence of events
      - enable and disable such interruptions as desired.
      - machine instructions such as Interrupt-enable and Interrupt-disable
    - - Multiple I/O devices , thus can generate multiple interrupt requests.
    - - IRQ bit which it sets to 1 when it requests an interrupt.
      - time consuming to query the status bits of all the I/O devices
      - priority is determined by the order in which the devices are polled.
    - - priority structure
      - Each device has its own interrupt request and interrupt acknowledge line.
      - A different priority level is assigned to the interrupt request line of each device.
  - - - Recovery from errors
      - Debugging
      - Privilege exception
    - - Using debugger
        
        Trace mode
        
        Breakpoints
- - - - fewer wires
      - physically distant
      - bit rate
      - range of clock speeds.
- - - - support memory transfers involve a burst of data rather than just one word.
      - Advantages
        
        Low cost bus
        
        Processor independent
        
        Plug and play capability
      - I/O Devices using PCI
        
        Grpahic Card/GPU
        
        Sound card
        
        High performance FPGA board
    - - Characteristics
        
        Two are used to carry power (+5V) and ground (Vbus, GND)
        
        The other two wires are used to carry data (D+, D-).
        
        Different signaling
        
        differential transmission
      - Root hub and appears as a single device
      - packets of information
      - 7-bit address
  - - - Initiate transaction
      - Identify device involved in transaction
      - Sourced by the host
    - - Delivers payload data
      - Sourced by host or device
    - - Acknowledge error-free data receipt
      - Sourced by receiver of data