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STM32F4 Discovery (Peripherals (UART (Modes (HW flow control (UART4, UART5…

- - - - Config register
        
        OTYPER, OSPEED: type & speed of output
        
        MODER: select input/output/analog/alt func mode
        
        PUPD: select pull up/down for input/output
      - Set/Reset register
        
        BSRR
      - Data register
        
        IDR (input data), ODR (output data)
      - Alternate function register
        
        AFRL, AFRH:
      - Locking register
        
        LCKR: lock control and alt func registers
    - - Schmitt trigger
        
        Not active in analog mode
        
        Convert analog to digital
      - 5-volt tolerant
        
        Protect the board
        
        prevent voltage from exceeding a certain range
        
        is not reach 5-volt in Analog mode
      - Register read/write
        
        Read-only: IDR
        
        Write-only: BSRR
        
        Read/Write: remaining
  - - - Needed things in SysTick implementation
        
        1 couting variable
        
        Func SysTick_Config(uint32_t time_to_gen_IRQ)
        
        Func SysTick_Handle(void)
        => handle each SysTick IRQ
        
        [optional] delay func
  - - - Status register
        
        SR
      - Data register
        
        DR
      - Baudrate register
        
        BRR
      - Control register
        
        CR1, CR2, CR3
        For basic config, just use CR1 + stop bit in CR2
      - Guard time and Prescaler register
        
        GTPR
    - - Asynchronous
      - HW flow control
        
        UART4, UART5 not support
      - DMA
      - Multi processor comm
      - Synchronous
        
        UART4, UART5 not support
      - Smartcard
        
        UART4, UART5 not support
      - Half-duplex (Single-wire)
      - IrDA
      - LIN
    - - Transmit
        
        TXE: transmit data reg empty
        
        Enabled by TXEIE
        
        Cleared by writting to data reg
        
        Set by HW when
        
        TDR reg is empty
        (TDR: transmit DR)
        
        data has been moved from TDR reg to Shift reg
        
        TC: transmit complete
        
        Cleared by
        
        Read from SR reg
        
        Write to DR reg
        
        Enabled by TCIE
        
        Set by setting TXE + transmission complete
        
        Misc
        
        TX interrupt use cases
        
        Sending multi bytes from a large-than-one-size buffer
      - Receive
        
        RXNE: received data ready to be read
        
        Set by
        
        data moved from Shift reg to RDR
        
        [Multi buffer mode] after each byte is received
        
        Cleared by
        
        [SIngle buffer mode] Read DR
        
        Write 0 to this bit
        
        [Multi buffer mode] read DR by DMA
        
        Enabled by RXNEIE