Please enable JavaScript.

Coggle requires JavaScript to display documents.

CHAPTER 3: INPUT/OUTPUT (1. BUS STRUCTURE & OPERATION (c) General Bus…

- - - - :point_right::skin-tone-2:processor
      - :point_right::skin-tone-2:main memory
      - :point_right::skin-tone-2:I/O devices
  - - - Versatility
        
        new devices can be added easily
      - Low cost
        
        a single set of wires is shared in multiple ways
    - - Communication bottleneck
      - Maximum bus speed largely limited
  - - - designate the source of destination of the data on the data bus
    - - provide a path for moving data
    - - control the access and the use of the data
  - - - responds to the address
    - - starts the transaction
- - - - requires hardware (arbiter) that will grant the bus to one of the requesting devices
    - - there isn't an arbiter, the I/O devices have to decide who goes next
  - - - master and slave operations are referenced to a clock
      - bus propagation delay
        
        :information_source: operations are referenced to the clock, but realistically, there will be delay in the communication
    - - data transfers are controlled by a handshake between the master and the slave (no common clock)
      - two timing control lines operations:
        
        master-ready :point_left::skin-tone-2:
        
        slave-ready :point_left::skin-tone-2:
- - - - an interrupt request from a high-priority device is accepted while the processor is executing the interrupt service routine of a low priority device
    - - encoded in a few bits of the processor status register
  - - - processor takes the same steps as in the case of I/O interrupt-request
      - suspends the execution of the current program
- - - - a number of bits at a time
    - - one bit at a time
- - - - Control: activate a peripheral
      - Test: test various status conditions
      - Read: obtain data
      - Write: transmit that data to the peripheral
  - - - limited by the speed of the I/O device
      - large volumes of data are to be moved
  - - - starting memory address
      - number of words in the block
      - direction of transfer
      - informs the processor once transfer is completed
    - - single-bus, detached DMA
      - single-bus, integrated DMA-I/O
      - I/O bus
- - - - support memory transfers involve a burst of data rather than just one word
      - advantages
        
        :!:low-cost bus
        
        :!:processor independent
        
        :!:plug-and-play capability
      - I/O devices
        
        :star:graphic card/GPU
        
        :star:sound card
        
        :star:high performance FPGA board
    - - industry standard
      - characteristics
        
        consist of four wires
        
        two wires are used to carry data
        
        differential transmission