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Logical Effort, Linear Delay Model - Coggle Diagram
Logical Effort
Multistage Logic Networks
Multi Branch
Path effort
F = BGH
H = C 끝 / C 시작
g 하나씩 곱
(Cin Branch)/(Cin Path)
Path Delay
f = (F)^(1/N)
D = SUM(f)+SUM(p)
Gate Size
뒤에서 부터
Best Number of Stage
FO4
Best Number of SIze
Linear Delay Model
D = gh + p
G : logical effort
C input / C inverter
Size 최소 후 생각
G = 1 (inverter)
Inverter Normalized Slope
H : electrical effort
C load / C in
Fanout
Normalized 줄기
(Load Tr Width 갯수)/(Input Tr Width 갯수)
P : Parasitic Delay
C output / C inv,output
사이즈 최소화 후 생각
No load
Inverter normalized delay 절편
T = D*(T invertor)
외울것
Parasitic Delay
NAND2 3 4 -> 2 3 4
NOR 2 3 4 -> 2 4 6
